SNAS791D December   2019  – February 2022 LMK1C1102 , LMK1C1103 , LMK1C1104

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Inputs
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
IDD Core supply current, static All-outputs disabled, fIN = 0 V 25 45 µA
IDD Core supply current All-outputs disabled, fIN = 100 MHz 8 15 mA
All-outputs active, fIN = 100 MHz, CL = 5pF, VDD = 1.8 V 14 20
All-outputs active, fIN = 100 MHz, CL = 5pF, VDD = 2.5 V 21 30
All-outputs active, fIN = 100 MHz, CL = 5pF, VDD = 3.3 V 33 40
CLOCK INPUT
fIN_SE Input frequency VDD = 3.3 V DC 250 MHz
VDD = 2.5 V and 1.8 V DC 200
VIH Input high voltage 0.7 x VDD V
VIL Input low voltage 0.3 x VDD
dVIN/dt Input slew rate 20% - 80% of input swing 0.1 V/ns
IIN_LEAK Input leakage current –50 50 uA
CIN_SE Input capacitance at 25°C 7 pF
CLOCK OUTPUT FOR ALL VDD LEVELS
fOUT Output frequency VDD = 3.3 V 250 MHz
VDD = 2.5 V and 1.8 V 200
ODC Output duty cycle With 50% duty cycle input (for all VDD) 45 55 %
tSTART Start-up time before output is active See (1) 3 ms
t1G_ON Output enable time See (2) 5 cycles
t1G_OFF Output disable time See (3) 5 cycles
CLOCK OUTPUT FOR VDD = 3.3 V ± 5%
VOH Output high voltage IOH = 1 mA 2.8 V
VOL Output low voltage IOL = 1 mA 0.2
tRISE-FALL Output rise and fall time 20/80%, CL= 5 pF, fIN = 156.25 MHz 0.35 0.7 ns
tOUTPUT-SKEW Output-output skew See (4) 25 50 ps
tPART-SKEW Part-to-part skew 250
tPROP-DELAY Propagation delay See (5) 1.5 2 ns
tJITTER-ADD Additive Jitter fIN = 156.25 MHz, Input slew rate = 2 V/ns, Integration range = 12 kHz - 20 MHz 8 20 fs, RMS
ROUT Output impedance 50 Ω
CLOCK OUTPUT FOR VDD = 2.5 V ± 5%
VOH Output high voltage IOH = 1 mA 0.8 x VDD V
VOL Output low voltage IOL = 1 mA 0.2 x VDD
tRISE-FALL Output rise and fall time 20/80%, CL= 5 pF, fIN = 156.25 MHz 0.33 0.8 ns
tOUTPUT-SKEW Output-output skew See (4) 50 ps
tPART-SKEW Part-to-part skew 400
tPROP-DELAY Propagation delay See (5) 1.5 2.5 ns
tJITTER-ADD Additive Jitter fIN = 156.25 MHz, Input slew rate = 2 V/ns, Integration range = 12 kHz - 20 MHz 11 27 fs, RMS
ROUT Output impedance 52.5 Ω
CLOCK OUTPUT FOR VDD = 1.8 V ± 5%
VOH Output high voltage IOH = 1 mA 0.8 x VDD V
VOL Output low voltage IOL = 1 mA 0.2 x VDD
tRISE-FALL Output rise and fall time 20/80%, CL= 5 pF, fIN = 156.25 MHz 0.38 1 ns
tOUTPUT-SKEW Output-output skew See (4) 50 ps
tPART-SKEW Part-to-part skew 900 ps
tPROP-DELAY Propagation delay See (5) 1.5 3 ns
tJITTER-ADD Additive Jitter fIN = 156.25 MHz, Input slew rate = 2 V/ns, Integration range = 12 kHz - 20 MHz 17.5 50 fs, RMS
ROUT Output impedance 60 Ω
GENERAL PURPOSE INPUT (1G)
VIH High-level input voltage 0.75 x VDD V
VIL Low-level input voltage 0.25 x VDD
IIH Input high-level current VIH = VDD_REF –50 50 µA
IIL Input low-level current VIL = GND –50 50
(1) Measured from VDD stable to output active, when 1G = HIGH.
(2) Measured from 1G rising edge crossing VIH to first rising edge of Yn.
(3) Measured from 1G falling edge crossing VIL to last falling edge of Yn.
(4) Measured from rising edge of any Yn output to any other Ym output.
(5) Measured from rising edge of CLKIN to any Yn output.