SNAS814A December   2020  – January 2022 LMK1C1106 , LMK1C1108

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3 Application Curves

The low additive jitter of the LMK1C110x is shown in Figure 9-2.

Figure 9-3 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x, resulting in 27.3-fs RMS jitter when integrated from 12 kHz to 20 MHz at 3.3-V supply. The resultant additive jitter measured is a low 11.4-fs RMS for this configuration.

Figure 9-4 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x, resulting in 29-fs RMS jitter when integrated from 12 kHz to 20 MHz at 2.5-V supply. The resultant additive jitter measured is a low 15-fs RMS for this configuration.

Figure 9-5 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x, resulting in 34-fs RMS jitter when integrated from 12 kHz to 20 MHz at 1.8-V supply. The resultant additive jitter measured is a low 23.25-fs RMS for this configuration.

GUID-20201203-CA0I-N45H-RZMF-5WD40H20JRR0-low.pngFigure 9-2 LMK1C110x Reference Phase Noise 24.8-fs (12 kHz to 20 MHz)
GUID-20201203-CA0I-SKFG-RRFK-NKZKQ5D0P5C7-low.pngFigure 9-4 LMK1C110x 2.5-V Output Phase Noise 29-fs (12 kHz to 20 MHz)
GUID-20201203-CA0I-SZGP-0JTT-LJT78V0FLQQJ-low.pngFigure 9-3 LMK1C110x 3.3-V Output Phase Noise 27.3-fs (12 kHz to 20 MHz)
GUID-20201203-CA0I-L3X9-66WW-PQB72PKSDZTC-low.pngFigure 9-5 LMK1C110x 1.8-V Output Phase Noise 34-fs (12 kHz to 20 MHz)