SNAS830A september   2021  – june 2023 LMK1D1204P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions


GUID-20211025-CA0I-5FTK-BXDB-VF4DFBMKCVQW-low.svg
Figure 6-1 LMK1D1204P: RHD Package 28-Pin VQFN Top View
Table 6-1 Pin Functions
NAME NO. TYPE(1) DESCRIPTION
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P 9 I Primary: Differential input pair or single-ended input
IN0_N 10
IN1_P 5 I Secondary: Differential input pair or single-ended input.

Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
IN1_N 6
INPUT SELECT
IN_SEL 2 I Input Selection with an internal 500-kΩ pullup and 320-kΩ pulldown, selects input port. See Table 9-1.
OUTPUT ENABLE
OE0 13 I Output Enable for channel 0
HIGH (default): Enable output channel 0
LOW: Disable output channel 0 in Hi-Z state
OE1 19 I Output Enable for channel 1
HIGH (default): Enable output channel 1
LOW: Disable output channel 1 in Hi-Z state
OE2 24 I Output Enable for channel 2
HIGH (default): Enable output channel 2
LOW: Disable output channel 2 in Hi-Z state
OE3 3 I Output Enable for channel 3
HIGH (default): Enable output channel 3
LOW: Disable output channel 3 in Hi-Z state
BIAS VOLTAGE OUTPUT
VAC_REF0 11 O Bias voltage output for capacitive-coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin.
VAC_REF1 7
DIFFERENTIAL CLOCK OUTPUT
OUT0_P 16 O Differential LVDS output pair number 0
OUT0_N 17
OUT1_P 20 O Differential LVDS output pair number 1
OUT1_N 21
OUT2_P 22 O Differential LVDS output pair number 2
OUT2_N 23
OUT3_P 26 O Differential LVDS output pair number 3
OUT3_N 27
SUPPLY VOLTAGE
VDD 8, 15, 28 P Device power supply (1.8 V, 2.5 V, or 3.3 V)
GROUND
GND 1, 14 G Ground
MISC
DAP DAP GND Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation.
NC 4, 12, 18, 25 NC No Connection. Leave floating
(1) G = Ground, I = Input, O = Output, P = Power