SNAS830A september   2021  – june 2023 LMK1D1204P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.2 Input Termination

The LMK1D1204P inputs can be interfaced with LVDS, LVPECL, HCSL, or LVCMOS drivers.

LVDS drivers can be connected to LMK1D1204P inputs with DC and AC coupling as shown Figure 9-3 and Figure 9-4, respectively.

GUID-94D60E06-64DF-463B-9861-14F312CF8010-low.gifFigure 9-3 LVDS Clock Driver Connected to LMK1D1204P Input (DC-Coupled)
GUID-0AA8BA37-E447-4148-BF2C-6A9A9C6D49AA-low.gifFigure 9-4 LVDS Clock Driver Connected to LMK1D1204P Input (AC-Coupled)

Figure 9-5 shows how to connect LVPECL inputs to the LMK1D1204P. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP.

GUID-6DB90B11-0483-4F76-9CF5-6FAC01681F08-low.gifFigure 9-5 LVPECL Clock Driver Connected to LMK1D1204P Input

Figure 9-6 shows how to couple a LVCMOS clock input to the LMK1D1204P directly.

GUID-20210622-CA0I-XK7S-L7BT-4RBG5F2NNFCP-low.svgFigure 9-6 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D1204P Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.