SNAS828A february   2022  – june 2023 LMK1D1208I

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input
      2. 9.3.2 Input Stage Configurability
      3. 9.3.3 Dual Output Bank
      4. 9.3.4 I2C
        1. 9.3.4.1 I2C Address Assignment
      5. 9.3.5 LVDS Output Termination
      6. 9.3.6 Input Termination
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Enable Control
      2. 9.4.2 Bank Input Selection
      3. 9.4.3 Bank Mute Control
      4. 9.4.4 Output Enable Control
      5. 9.4.5 Output Amplitude Selection
    5. 9.5 Programming
    6. 9.6 Register Maps
      1. 9.6.1 LMK1D1208I Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

VDD = 1.8 V ± 5 %, –40°C ≤ TA ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY CHARACTERISTICS
IDDSTAT LMK1D1208I All-outputs enabled and unterminated, f = 0 Hz (AMP_SEL =1) 55 mA
IDD100M LMK1D1208I All-outputs enabled, RL = 100 Ω, f =100 MHz (AMP_SEL = 0, default) 75 95 mA
IDD100M LMK1D1208I All-outputs enabled, RL = 100 Ω, f =100 MHz, AMP_SEL = 1 110 mA
IDX INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
VIH Input high voltage Minimum input voltage for a logical "1" state 0.7 × VCC VCC + 0.3 V
VIL Input low voltage Maximum input voltage for a logical "0" state –0.3 0.3 × VCC V
IIH Input high current VDD can be 1.8V/2.5V/3.3V with VIH = VDD 30 µA
IIL Input low current VDD can be 1.8V/2.5V/3.3V with VIH = VDD –30 µA
Rpull-up(IDX) Input pullup resistor 670 kΩ
I2C INTERFACE CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
VIH Input high voltage 0.7 × VCC VCC + 0.3 V
VIL Input low voltage –0.3 0.3 × VCC V
IIH Input high current 30 µA
IIL Input low current –30 µA
CIN_SE Input capacitance at 25°C 2 pF
VOL Output low voltage IOL = 3 mA 0.3 V
fSCL I2C clock rate Standard 100 kHz
Fast mode 400
Ultra Fast mode 1000
tSU(START) START condition setup time SCL high before SDA low 0.6 us
tH(START) START condition hold time SCL low after SDA low 0.6 us
tW(SCLH) SCL pulse width high 0.6 us
tW(SCLL) SCL pulse width low 1.3 us
tSU(SDA) SDA setup time 100 ns
tH(SDA) SDA hold time SDA valid after SCL low 0 0.9 us
tR(IN) SDA/SCL input rise time 300 ns
tF(IN) SDA/SCL input fall time 300 ns
tF(OUT) SDA output fall time CBUS <= 400 pF 300 ns
tSU(STOP) STOP condition setup time 0.6 us
tBUS Bus free time between STOP and START 1.3 us
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN Input frequency Clock input DC 250 MHz
VIN_S-E Single-ended Input Voltage Swing Assumes a square wave input with two levels 0.4 3.465 V
dVIN/dt Input Slew Rate (20% to 80% of the amplitude) 0.05 V/ns
IIH Input high current VDD = 3.465 V, VIH = 3.465 V 50 µA
IIL Input low current VDD = 3.465 V, VIL = 0 V –30 µA
CIN_SE Input capacitance at 25°C 3.5 pF
DIFFERENTIAL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN Input frequency Clock input 2 GHz
VIN,DIFF(p-p) Differential input voltage peak-to-peak {2*(VINP-VINN)} VICM = 1 V (VDD = 1.8 V) 0.3 2.4 VPP
VICM = 1.25 V (VDD = 2.5 V/3.3 V) 0.3 2.4
VICM Input common mode voltage VIN,DIFF(P-P) > 0.4 V (VDD = 1.8 V/2.5/3.3 V) 0.25 2.3 V
IIH Input high current VDD = 3.465 V, VINP = 2.4 V, VINN = 1.2 V 30 µA
IIL Input low current VDD = 3.465 V, VINP = 0 V, VINN = 1.2 V –30 µA
CIN_S-E Input capacitance (Single-ended) at 25°C 3.5  pF
LVDS DC OUTPUT CHARACTERISTICS
|VOD| Differential output voltage magnitude |VOUTP - VOUTN| VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 0 250 350 450 mV
|VOD| Differential output voltage magnitude |VOUTP - VOUTN| VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 400 500 650 mV
ΔVOD Change in differential output voltage magnitude. Per output, defined as the difference between VOD in logic hi/lo states. VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 0 –15 15 mV
ΔVOD Change in differential output voltage magnitude VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 –20 20 mV
VOC(SS) Steady-state common mode output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 1.8 V) 1 1.2 V
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 2.5 V/3.3 V) 1.1 1.375
VOC(SS) Steady-state common mode output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 1.8 V), AMP_SEL = 1 0.8 1 V
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 2.5 V/3.3 V), AMP_SEL = 1 0.9 1.1
ΔVOC(SS) Change in steady-state common mode output voltage. Per output, defined as the difference in VOC in logic hi/lo states. VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 0 –15 15 mV
ΔVOC(SS) Change in steady-state common mode output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 –20 20 mV
LVDS AC OUTPUT CHARACTERISTICS
Vring Output overshoot and undershoot VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, fOUT = 491.52 MHz –0.1 0.1 VOD
VOS Output AC common mode VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω , AMP_SEL = 0 50 100 mVpp
VOS Output AC common mode VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 75 150 mVpp
IOS Short-circuit output current (differential) VOUTP = VOUTN –12 12 mA
IOS(cm) Short-circuit output current (common-mode) VOUTP = VOUTN = 0 –24 24 mA
tPD Propagation delay VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (2) 0.3 0.575 ns
tSK, O Output skew Skew between outputs with the same load conditions (4 and 8 channel) (3) 20 ps
tSK, PP Part-to-part skew Skew between outputs on different parts subjected to the same operating conditions with the same input and output loading. 250 ps
tSK, P Pulse skew 50% duty cycle input, crossing point-to-crossing-point distortion (4) –20 20 ps
tRJIT(ADD) Random additive Jitter (rms) fIN = 156.25 MHz with 50% duty-cycle, Input slew rate = 1.5V/ns, Integration range = 12 kHz – 20 MHz, with output load RLOAD = 100 Ω  50 60 fs, RMS
Phase noise Phase Noise for a carrier frequency of 156.25 MHz with 50% duty-cycle, Input slew rate = 1.5V/ns with output load RLOAD = 100 Ω PN1kHz  –143 dBc/Hz
PN10kHz  –152
PN100kHz –157
PN1MHz  –160
PNfloor  –164
MUXISO Mux Isolation fIN = 156.25 MHz. The difference in power level at fIN when the selected clock is active and the unselected clock is static versus when the selected clock is inactive and the unselected clock is active. 80 dB
ODC Output duty cycle With 50% duty cycle input 45 55 %
tR/tF Output rise and fall time 20% to 80% with RLOAD = 100 Ω 300 ps
tR/tF Output rise and fall time 20% to 80% with RLOAD = 100 Ω (AMP_SEL= 1) 300 ps
ten/disable Output Enable and Disable Time Time taken for outputs to go from disable state to enable state and vice versa. (5) (6) 1 us
IleakZ Output leakage current in High Z Outputs are held in high Z mode with OUTP = OUTN (max applied external voltage is the lesser of VDD or 1.89V and minimum applied external voltage is 0V 50 uA
VAC_REF Reference output voltage VDD = 2.5 V, ILOAD = 100 µA 0.9 1.25 1.375 V
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V
PSNR Power Supply Noise Rejection (fcarrier = 156.25 MHz) 10 kHz, 100 mVpp ripple injected on VDD –70 dBc
1 MHz, 100 mVpp ripple injected on VDD –50
(1) Measured between single-ended/differential input crossing point to the differential output crossing point.
(2) For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.
(3) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
(4) Applies to the dual bank family.
(5) Time starts after the acknowledge bit