SNAS823A october   2021  – april 2023 LMK1D1212 , LMK1D1216

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input and Hysteresis
      2. 9.3.2 Input Mux
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions


GUID-20230221-SS0I-4WWQ-1KS9-16GQ2Z3447M6-low.svg
Figure 6-1 LMK1D1212: RHA Package 40-Pin VQFN Top View

GUID-20230221-SS0I-CHK5-TBMV-2TQ3XXJM8WKD-low.svg
Figure 6-2 LMK1D1216: RGZ Package 48-Pin VQFN Top View
Table 6-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMELMK1D1212LMK1D1216
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P

9

10

IPrimary: Differential input pair or single-ended input
IN0_N

8

9

IN1_P23ISecondary: Differential input pair or single-ended input.

Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.

IN1_N34
INPUT SELECT
IN_SEL12IInput Selection with an internal 500-kΩ pullup and 320-kΩ pulldown resistor; selects input port. See Table 9-2.
AMPLITUDE SELECT
AMP_SEL1011IOutput amplitude swing select with an internal 500-kΩ pullup and 320-kΩ pulldown. See Table 9-3.
BIAS VOLTAGE OUTPUT
VAC_REF078OBias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin.
VAC_REF145
DIFFERENTIAL CLOCK OUTPUT
OUT0_P1214ODifferential LVDS output pair number 0
OUT0_N1315
OUT1_P1416 ODifferential LVDS output pair number 1
OUT1_N1517
OUT2_P1618ODifferential LVDS output pair number 2
OUT2_N1719
OUT3_P1820ODifferential LVDS output pair number 3
OUT3_N1921
OUT4_P2222ODifferential LVDS output pair number 4
OUT4_N2323
OUT5_P2425ODifferential LVDS output pair number 5
OUT5_N2526
OUT6_P2627ODifferential LVDS output pair number 6
OUT6_N2728
OUT7_P2829ODifferential LVDS output pair number 7
OUT7_N2930
OUT8_P3231ODifferential LVDS output pair number 8
OUT8_N3332
OUT9_P3433ODifferential LVDS output pair number 9
OUT9_N3534
OUT10_P3635ODifferential LVDS output pair number 10
OUT10_N3736
OUT11_P3838 ODifferential LVDS output pair number 11
OUT11_N3939
OUT12_P —40ODifferential LVDS output pair number 12
OUT12_N—41
OUT13_P—42ODifferential LVDS output pair number 13
OUT13_N—43
OUT14_P—44ODifferential LVDS output pair number 14
OUT14_N—45
OUT15_P—46ODifferential LVDS output pair number 15
OUT15_N—47
SUPPLY VOLTAGE
VDD5, 6, 11, 20, 31, 406, 7, 13, 24, 37, 48PDevice power supply (1.8 V, 2.5 V, or 3.3 V)
GROUND
GND21, 301, 12GGround
MISC
DAPDAPDAPGDie Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation.
(1) G = Ground, I = Input, O = Output, P = Power