SNAS888A September   2024  – November 2024 LMK1D2102L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Common Mode
      2. 8.3.2 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Enable / Disable and Amplitude Selection
      2. 8.4.2 LVDS Output Termination
      3. 8.4.3 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Detailed Design Procedure

See Input Termination for proper input terminations, dependent on single-ended or differential inputs.

See LVDS Output Termination for output termination schemes depending on the receiver application.

TI recommends unused outputs to be terminated differentially with a 100Ω resistor for optimum performance, although unterminated outputs are also okay but result in slight degradation in performance (Output AC common-mode VOS) in the outputs being used.

In this application example, the ADC clock and SYSREF clocks require different output interfacing schemes. Power-supply filtering and bypassing is critical for low-noise applications.

LMK1D210xL offers multiple output common range to meet receiver requirement for an ADC or AFEs. In case of common-mode mismatch between the output voltage of the LMK1D210xL and the receiver, use AC coupling to fix the mismatch. AC coupling adds settling time associated with this AC-coupling network (High-pass filter), which can result in non-deterministic behavior during the initial transients. For such applications, DC-coupling the outputs is necessary and thus requires a scheme which can overcome the inherent mismatch between the common-mode voltage of the driver and receiver.

The application note Interfacing LVDS Driver With a Sub-LVDS Receiver discusses how to interface between a LVDS driver and sub-LVDS receiver. The same concept can be applied to interface the LMK1D210xL outputs to a receiver which has a lower common-mode voltage.

LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L Schematic for DC-Coupling LMK1D210x With Lower Common-Mode ReceiverFigure 9-2 Schematic for DC-Coupling LMK1D210x With Lower Common-Mode Receiver

Figure 9-2 shows the resistor divider network for stepping down the common-mode voltage as explained in the previously mentioned application note. The resistors R1, R2 and R3 are selected according to the input common-mode voltage requirements of the receiver. As highlighted before, verify that the reduced swing is able to meet the requirements of the receiver. Higher swing mode (boosted LVDS swing mode) can be selected using the AMP_SEL pin highlighted in Section 8.4.1 to compensate for the reduced swing as the result of the resistor voltage divider.