SNAS888A September 2024 – November 2024 LMK1D2102L , LMK1D2104L , LMK1D2106L
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The LMK1D210xL is a low noise dual clock buffer which distributes one input to a maximum of 2 (LMK1D2102L), 4 (LMK1D2104L), 6 (LMK1D2106L) or 8 (LMK1D2108L) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.
The LMK1D210xL is specifically designed for driving 50Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-8).
LMK1D210xL buffer offers two output common mode operation (0.7V and 1.2V) for different operating supply. The device provides flexibility in design for DC-coupled mode applications.
AMP_SELA / AMP_SELB control pin can be used to select different output amplitude LVDS (350mV) or boosted LVDS (500mV). In addition to amplitude selection, outputs can be disabled using the same pin.
The part also supports Fail-Safe Input function for clock and digital input pins. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
PART NUMBER(1) | PACKAGE | PACKAGE SIZE(3) |
---|---|---|
LMK1D2102L | RGT (VQFN, 16) | 3.00mm × 3.00mm |
LMK1D2104L | RHD (VQFN, 28) | 5.00mm × 5.00mm |
LMK1D2106L | RHA (VQFN, 40) | 6.00mm × 6.00mm |
LMK1D2108L(2) | RGZ (VQFN, 48) | 7.00mm × 7.00mm |
DEVICE | DEVICE TYPE | FEATURES | OUTPUT SWING | OUTPUT COMMON MODE | PACKAGE | PACKAGE SIZE |
---|---|---|---|---|---|---|
LMK1D2102L | Dual 1:2 | Global output bank enable and swing control pin. | 350mV | 0.7V(2) | VQFN (16) | 3.00mm × 3.00mm |
1.2V | ||||||
500mV | 0.7V(2) | |||||
1V | ||||||
LMK1D2104L | Dual 1:4 | Global output bank enable and swing control pin. | 350mV | 0.7V(2) | VQFN (28) |
5.00mm × 5.00mm |
1.2V | ||||||
500mV | 0.7V(2) | |||||
1V | ||||||
LMK1D2106L | Dual 1:6 | Individual output bank enable and swing control pin. | 350mV | 0.7V(2) | VQFN (40) |
6.00mm × 6.00mm |
1.2V | ||||||
500mV | 0.7V(2) | |||||
1V | ||||||
LMK1D2108L | Dual 1:6 | Individual output bank enable and swing control pin. | 350mV | 0.7V(2) | VQFN (48) | 7.00mm × 7.00mm |
1.2 | ||||||
500mV | 0.7V(2) | |||||
1V | ||||||
LMK1D2102 | Dual 1:2 | Global output enable control through pin control | 350mV | 1.2V | VQFN (16) | 3.00mm × 3.00mm |
LMK1D2104 | Dual 1:4 | Global output enable control through pin control | 350mV | 1.2V | VQFN (28) | 5.00mm × 5.00mm |
LMK1D2106 | Dual 1:6 | Global output enable and swing control through pin control | 350mV | 1.2V | VQFN (40) | 6.00mm × 6.00mm |
500mV | 1V | |||||
LMK1D2108 | Dual 1:8 | Global output enable and swing control through pin control | 350mV | 1.2V | VQFN (48) | 7.00mm × 7.00mm |
500mV | 1V | |||||
LMK1D1204 | 2:4 | Global clock input selection and output enable control through pin control | 350mV | 1.2V | VQFN (16) | 3.00mm × 3.00mm |
LMK1D1204P | 2:4 | Individual output enable control through pin control | 350mV | 1.2V | VQFN (28) | 5.00mm × 5.00mm |
LMK1D1208 | 2:8 | Global clock input selection and output enable control through pin control | 350mV | 1.2V | VQFN (28) | 5.00mm × 5.00mm |
LMK1D1208P | 2:8 | Individual output enable control through pin control | 350mV | 1.2V | VQGN (40) |
6.00mm × 6.00mm |
500mV | 1V | |||||
LMK1D1208I | 2:8 | Individual output enable, swing, bank and clock input selection control through I2C | 350mV | 1.2V | VQFN (40) |
6.00mm × 6.00mm |
500mV | 1V | |||||
LMK1D1212 | 2:12 | Global output enable and swing control through pin control | 350mV | 1.2V | VQFN (40) | 6.00mm × 6.00mm |
500mV | 1V | |||||
LMK1D1216 | 2:16 | Global output enable and swing control through pin control | 350mV | 1.2V | VQFN (48) | 7.00mm × 7.00mm |
500mV | 1V | |||||
LMK1D1204I(1) | 2:4 | Individual output enable, swing, bank and clock input selection control through I2C | 350mV | 1.2V | VQFN (16) | 3.00mm × 3.00mm |
500mV | 1V | |||||
LMK1D1212I(1) | 2:12 | Individual output enable, swing, bank and clock input selection control through I2C | 350mV | 1.2V | VQFN (40) | 6.00mm × 6.00mm |
500mV | 1V | |||||
LMK1D1216I(1) | 2:16 | Individual output enable, swing, bank and clock input selection control through I2C | 350mV | 1.2V | VQFN (48) | 7.00mm × 7.00mm |
500mV | 1V | |||||
LMK1D1204L(1) | 2:4 | Global output bank enable and swing control pin. | 350mV | 0.7V(2) | VQFN (16) | 3.00mm × 3.00mm |
1.2V | ||||||
LMK1D1208L(1) | 2:8 | Global output bank enable and swing control pin. | 350mV | 0.7V(2) | VQFN (28) | 5.00mm × 5.00mm |
1.2V | ||||||
LMK1D1208PL(1) | 2:8 | Individual output enable control through pin control | 350mV | 0.7V(2) | VQFN (40) | 6.00mm × 6.00mm |
1.2V | ||||||
500mV | 0.7V(2) | |||||
1V | ||||||
LMK1D1212L(1) | 2:12 | Individual output bank enable and swing control pin. | 350mV | 0.7V(2) | VQFN (40) | 6.00mm × 6.00mm |
1.2V | ||||||
500mV | 0.7V(2) | |||||
1V | ||||||
LMK1D1216L(1) | 2:16 | Individual output bank enable and swing control pin. | 350mV | 0.7V(2) | VQFN (48) | 7.00mm × 7.00mm |
1.2V | ||||||
500mV | 0.7V(2) | |||||
1V | ||||||
LMK1D1212IL(1) | 2:12 | Individual output enable, swing, bank and clock input selection control through I2C | 350mV | 0.7V(2) | VQFN (40) | 6.00mm × 6.00mm |
1V | ||||||
500mV | 0.7V(2) | |||||
1V | ||||||
LMK1D1216IL(1) | 2:16 | Individual output enable, swing, bank and clock input selection control through I2C | 350mV | 0.7V(2) | VQFN (48) | 7.00mm × 7.00mm |
1.2V | ||||||
500mV | 0.7V(2) | |||||
1V |
PIN | TYPE(1) | DESCRIPTION | ||||
---|---|---|---|---|---|---|
NAME | LMK1D2102L | LMK1D2104L | LMK1D2106L | LMK1D2108L | ||
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT | ||||||
IN0_P, IN0_N | 6, 7 | 9, 10 | 9, 8 | 10, 9 | I | Primary: Differential input pair or single-ended input |
IN1_P, IN1_N | 3, 4 | 5, 6 | 2, 3 | 3, 4 | I | Secondary: Differential input pair or single-ended input |
Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N. | ||||||
BANK ENABLE AND AMPLITUDE SELECT | ||||||
AMP_SELA | 2 | 4 | 10 | 11 | I | Output bank enable/disable with an internal 500kΩ pullup and 320kΩ pulldown; (See Section 8.4.1) |
AMP_SELB | - | - | 1 | 2 | I | Output bank enable/disable with an internal 500kΩ pullup and 320kΩ pulldown; (See Section 8.4.1) |
BIAS VOLTAGE OUTPUT | ||||||
VAC_REF0 | 8 | 11 | 7 | 8 | O | Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1µF capacitor to GND on this pin. |
VAC_REF1 | - | - | 4 | 5 | O | Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1µF capacitor to GND on this pin. |
DIFFERENTIAL CLOCK OUTPUT | ||||||
OUT0_P, OUT0_N | 9, 10 | 12, 13 | 12, 13 | 14, 15 | O | Differential LVDS output pair number 0 |
OUT1_P, OUT1_N | 11, 12 | 16, 17 | 14, 15 | 16, 17 | O | Differential LVDS output pair number 1 |
OUT2_P, OUT2_N | 13, 14 | 18, 19 | 16, 17 | 18, 19 | O | Differential LVDS output pair number 2 |
OUT3_P, OUT3_N | 15, 16 | 20, 21 | 18, 19 | 20, 21 | O | Differential LVDS output pair number 3 |
OUT4_P, OUT4_N | - | 22, 23 | 22, 23 | 22, 23 | O | Differential LVDS output pair number 4 |
OUT5_P, OUT5_N | - | 24, 25 | 24, 25 | 25, 26 | O | Differential LVDS output pair number 5 |
OUT6_P, OUT6_N | - | 26, 27 | 26, 27 | 27, 28 | O | Differential LVDS output pair number 6 |
OUT7_P, OUT7_N | - | 2, 3 | 28, 29 | 29, 30 | O | Differential LVDS output pair number 7 |
OUT8_P, OUT8_N | - | - | 32, 33 | 31, 32 | O | Differential LVDS output pair number 8 |
OUT9_P, OUT9_N | - | - | 34, 35 | 33, 34 | O | Differential LVDS output pair number 9 |
OUT10_P, OUT10_N | - | - | 36, 37 | 35, 36 | O | Differential LVDS output pair number 10 |
OUT11_P, OUT11_N | - | - | 38, 39 | 38, 39 | O | Differential LVDS output pair number 11 |
OUT12_P, OUT12_N | - | - | - | 40, 41 | O | Differential LVDS output pair number 12 |
OUT13_P, OUT13_N | - | - | - | 42, 43 | O | Differential LVDS output pair number 13 |
OUT14_P, OUT14_N | - | - | - | 44, 45 | O | Differential LVDS output pair number 14 |
OUT15_P, OUT15_N | - | - | - | 46, 47 | O | Differential LVDS output pair number 15 |
SUPPLY VOLTAGE | ||||||
VDD | 5 | 8, 15, 28 | - | - | P | Device power supply (1.8V, 2.5V, or 3.3V) for Bank 0 and Bank 1 |
VDDA | - | - | 6, 11, 20 | 7, 13, 24 | P | Device power supply (1.8V, 2.5V, or 3.3V) for Bank 0 |
VDDB | - | - | 5, 31, 40 | 6, 37, 48 | P | Device power supply (1.8V, 2.5V, or 3.3V) for Bank 1 |
GROUND | ||||||
GND | 1 | 1, 14 | 21, 30 | 1, 12 | G | Ground |
MISC | ||||||
DAP | DAP | DAP | DAP | DAP | G | Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Supply voltage | –0.3 | 3.6 | V |
VIN | Input voltage | –0.3 | 3.6 | V |
VO | Output voltage | –0.3 | VDD + 0.3 | V |
IIN | Input current | –20 | 20 | mA |
IO | Continuous output current | –50 | 50 | mA |
TJ | Junction temperature | 135 | °C | |
Tstg | Storage temperature (2) | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±3000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VDD | Core supply voltage | 3.3V supply | 3.135 | 3.3 | 3.465 | V |
2.5V supply | 2.375 | 2.5 | 2.625 | |||
1.8V supply | 1.71 | 1.8 | 1.89 | |||
Supply Ramp | Supply voltage ramp | Requires monotonic ramp (10-90% of VDD) | 0.1 | 20 | ms | |
TA | Operating free-air temperature | –40 | 105 | °C | ||
TJ | Operating junction temperature | –40 | 135 | °C |
THERMAL METRIC (1) | LMK1D2102L | LMK1D2104L | LMK1D2106L | LMK1D2108L | UNIT | |
---|---|---|---|---|---|---|
VQFN | VQFN | VQFN | VQFN | |||
16 PINS | 28 PINS | 40 PINS | 48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 48.7 | 38.9 | 30.3 | 30.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 56.4 | 32.1 | 21.6 | 21.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 23.6 | 18.7 | 13.1 | 12.9 | °C/W |
ΨJT | Junction-to-top characterization parameter | 1.6 | 1 | 0.4 | 0.4 | °C/W |
ΨJB | Junction-to-board characterization parameter | 23.6 | 18.7 | 13 | 12.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 8.6 | 8.2 | 4.5 | 4.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY CHARACTERISTICS | ||||||
IDD100M | LMK1D2102L | All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA = 0 | 70 | 80 | mA | |
IDD100M | LMK1D2104L | All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA = 0 | 80 | 105 | mA | |
IDD100M | LMK1D2106L | All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA and AMP_SELB = 0 | 113 | 140 | mA | |
IDD100M | LMK1D2108L | All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA and AMP_SELB = 0 | 134 | 160 | mA | |
IDD100M | LMK1D2102L | All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA = Float | 75 | 87 | mA | |
IDD100M | LMK1D2104L | All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA = Float | 85 | 115 | mA | |
IDD100M | LMK1D2106L | All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA and AMP_SELB = Float | 134 | 160 | mA | |
IDD100M | LMK1D2108L | All-outputs enabled, RL = 100Ω, f =100MHz, AMP_SELA and AMP_SELB = Float | 155 | 180 | mA | |
IDDPOWER DOWN | LMK1D2102L | All-outputs disabled and unterminated, AMP_SELA = 1 | 50 | mA | ||
IDDPOWER DOWN | LMK1D2102L | All-outputs disabled, RL = 100Ω, AMP_SELA = 1 | 65 | mA | ||
IDDPOWER DOWN | LMK1D2104L | All-outputs disabled and unterminated, AMP_SELA = 1 | 55 | mA | ||
IDDPOWER DOWN | LMK1D2104L | All-outputs disabled, RL = 100Ω, AMP_SELA = 1 | 80 | mA | ||
IDDPOWER DOWN | LMK1D2106L | All-outputs disabled and unterminated, AMP_SELA and AMP_SELB = 1 | 75 | mA | ||
IDDPOWER DOWN | LMK1D2106L | All-outputs disabled, RL = 100Ω, AMP_SELA and AMP_SELB = 1 | 110 | mA | ||
IDDPOWER DOWN | LMK1D2108L | All-outputs disabled and unterminated, AMP_SELA and AMP_SELB = 1 | 80 | mA | ||
IDDPOWER DOWN | LMK1D2108L | All-outputs disabled, RL = 100Ω, AMP_SELA and AMP_SELB = 1 | 130 | mA | ||
AMP_SELA / AMP_SELB INPUT CHARACTERISTICS | ||||||
VdI3 | 3-state input | Open / floating | 0.4*VCC | V | ||
VIH | Input high voltage | Minimum input voltage for a logical "1" state | 0.7*VCC | VCC + 0.3 | V | |
VIL | Input low voltage | Maximum input voltage for a logical "0" state | –0.3 | 0.3*VCC | V | |
IIH | Input high current | VDD can be 1.8V/2.5V/3.3V with VIH = VDD | 30 | µA | ||
IIL | Input low current | VDD can be 1.8V/2.5V/3.3V with VIH = VDD | –30 | µA | ||
Rpull-up | Input pullup resistor (AMP_SELA, AMP_SELB) | 500 | kΩ | |||
Rpull-down | Input pulldown resistor (AMP_SELA, AMP_SELB) | 320 | kΩ | |||
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT | ||||||
fIN | Input frequency | Clock input | DC | 250 | MHz | |
VIN_S-E | Single-ended Input Voltage Swing | Assumes a square wave input with two levels | 0.4 | 3.465 | VPP | |
dVIN/dt | Input Slew Rate (20% to 80% of the amplitude) | 0.05 | V/ns | |||
IIH | Input high current | VDD = 3.465V, VIH = 3.465V | 50 | µA | ||
IIL | Input low current | VDD = 3.465V, VIL = 0V | -30 | µA | ||
CIN_SE | Input capacitance | at 25°C | 3.5 | pF | ||
DIFFERENTIAL CLOCK INPUT | ||||||
fIN | Input frequency | Clock input | 2 | GHz | ||
VIN,DIFF(p-p) | Differential input voltage peak-to-peak {2*(VINP-VINN)} | VICM = 1V (VDD = 1.8V) | 0.3 | 2.4 | VPP | |
VICM = 1.25V (VDD = 2.5V/3.3V) | 0.3 | 2.4 | ||||
VICM | Input common mode voltage | VIN,DIFF(P-P) > 0.4V (VDD = 1.8V/2.5V/3.3V) | 0.25 | 2.3 | V | |
IIH | Input high current | VDD = 3.465V, VINP = 2.4V, VINN = 1.2V | 30 | µA | ||
IIL | Input low current | VDD = 3.465 V, VINP = 0V, VINN = 1.2V | –30 | µA | ||
CIN_S-E | Input capacitance (Single-ended) | at 25°C | 3.5 | pF | ||
LVDS DC OUTPUT CHARACTERISTICS | ||||||
|VOD| | Differential output voltage magnitude |VOUTP - VOUTN| | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = 0 | 250 | 350 | 450 | mV |
|VOD| | Differential output voltage magnitude |VOUTP - VOUTN| | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = Float | 400 | 500 | 650 | mV |
ΔVOD | Change in differential output voltage magnitude. Per output, defined as the difference between VOD in logic hi/lo states. | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = 0 | –15 | 15 | mV | |
ΔVOD | Change in differential output voltage magnitude | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = Float | –20 | 20 | mV | |
VOC(SS) | Steady-state common mode output voltage | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 1.8V, AMP_SELA, AMP_SELB = 0 | 0.6 | 0.7 | 0.8 | V |
VOC(SS) | Steady-state common mode output voltage (LMK1D2104L, LMK1D2106L, LMK1D2108L) | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 1.8V, AMP_SELA, AMP_SELB = Float | 0.6 | 0.7 | 0.8 | V |
VOC(SS) | Steady-state common mode output voltage (LMK1D2102L) | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 1.8V, AMP_SELA, AMP_SELB = Float, TA = -40℃ to 105℃ | 0.6 | 0.7 | 0.82 | V |
VOC(SS) | Steady-state common mode output voltage (LMK1D2102L) | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 1.8V, AMP_SELA, AMP_SELB = Float, TA = -40℃ to 85℃ | 0.6 | 0.7 | 0.8 | V |
VOC(SS) | Steady-state common mode output voltage | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 2.5V/3.3V, AMP_SELA, AMP_SELB = 0 | 1.1 | 1.375 | V | |
VOC(SS) | Steady-state common mode output voltage | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, VDD = 2.5V/3.3V, AMP_SELA, AMP_SELB = Float | 0.9 | 1.15 | V | |
ΔVOC(SS) | Change in steady-state common mode output voltage | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = 0 | –15 | -15 | mV | |
ΔVOC(SS) | Change in steady-state common mode output voltage | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = Float | –20 | 20 | mV | |
LVDS AC OUTPUT CHARACTERISTICS | ||||||
Vring | Output overshoot and undershoot | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, fOUT ≤ 491.52MHz | –0.1 | 0.1 | VOD | |
VOS | Output AC common mode | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = 0 | 50 | 100 | mVpp | |
VOS | Output AC common mode | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω, AMP_SELA, AMP_SELB = Float | 75 | 150 | mVpp | |
VOS | Output AC common mode | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω | 50 | 100 | mVpp | |
IOS | Short-circuit output current (differential) | VOUTP = VOUTN | –12 | 12 | mA | |
IOS(cm) | Short-circuit output current (common-mode) | VOUTP = VOUTN = 0 | –24 | 24 | mA | |
tPD | Propagation delay | VIN,DIFF(P-P) = 0.3VPP, RL = 100Ω (1) | 0.3 | 0.575 | ns | |
tSK, O | Output skew | Skew between outputs with the same load conditions | 20 | ps | ||
tSK, b | Output bank skew | Skew between the outputs within the same bank (2102L/2104L) (2) | 15 | ps | ||
tSK, b | Output bank skew | skew between the outputs within the same bank (2106L/2108L) (2) | 17.5 | ps | ||
tSK, PP | Part-to-part skew | Skew between outputs on different parts subjected to the same operating conditions with the same input and output loading. | 150 | ps | ||
tSK, P | Pulse skew | 50% duty cycle input, crossing point-to-crossing-point distortion (2) | –20 | 20 | ps | |
tRJIT(ADD) | Random additive Jitter (rms) | fIN = 156.25MHz with 50% duty-cycle, Input slew rate = 1.5V/ns, Integration range = 12kHz - 20MHz, with output load RL = 100Ω | 45 | 60 | fs, RMS | |
Phase noise | Phase Noise for a carrier frequency of 156.25MHz with 50% duty-cycle, Input slew rate = 1.5V/ns with output load RL= 100Ω | PN1kHz | –143 | dBc/Hz | ||
PN10kHz | -152 | |||||
PN100kHz | -157 | |||||
PN1MHz | -160 | |||||
PNfloor | –164 | |||||
MUXISO | Mux Isolation | fIN = 156.25MHz. The difference in power level at fIN when the selected clock is active and the unselected clock is static versus when the selected clock is inactive and the unselected clock is active. | 80 | dB | ||
SPUR | Spurious suppression between dual banks | Differential inputs with FIN0 = 491.52MHz, FIN1 = 61.44MHz; Measured between neighboring outputs | –60 | dB | ||
Different inputs with FIN0 = 491.52MHz, FIN1 = 15.36MHz; Measured between neighboring outputs | –70 | |||||
ODC | Output duty cycle | With 50% duty cycle input | 45 | 55 | % | |
tR/tF | Output rise and fall time | 20% to 80% with RL = 100Ω | 300 | ps | ||
VAC_REF | Reference output voltage | VDD = 2.5V, ILOAD = 100µA | 0.9 | 1.25 | 1.375 | V |
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5V / 3.3V | ||||||
PSNR | Power Supply Noise Rejection (fcarrier = 156.25MHz) | 10kHz, 100mVpp ripple injected on VDD | –95 | dBc | ||
1MHz, 100mVpp ripple injected on VDD | –75 |
LMK1D210xL buffer typical characteristics are shown for current consumption, phase noise performance and timing diagrams and output common mode operation.
Note that these graphs serve as a guidance to the users on what to expect for the range of operating frequency supported by the LMK1D210xL. These graphs are plotted for a limited number of frequencies and load conditions, which do not represent the customer system.
See Note 1 and 2 in Graph Notes table | ||
See Note 1 and 3 in Graph Notes table | ||
See Note 1 and 4 in Graph Notes table | ||
NOTE | ||||
---|---|---|---|---|
(1) | The typical RMS jitter values in the plots show the total output RMS jitter (JOUT) for each frequency and the source clock RMS jitter (JSOURCE). From these values, the Additive RMS Jitter can be calculated as: JADD = SQRT(JOUT2 – JSOURCE2). | |||
(2) | JADD at 156.25MHz = SQRT(46.9322- 25.0572) = 39.68fs. | |||
(3) | JADD at 625MHz = SQRT(23.4382- 8.4332) = 21.87fs. | |||
(4) | JADD at 1250MHz = SQRT(17.8592- 6.7762) = 16.52fs. |