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Data Sheet
LMK1D210xL Ultra Low
Additive Jitter LVDS Buffer
1 Features
- High-performance LVDS clock buffer family: up to
2GHz
- Dual 1:2 differential buffer
- Dual 1:4 differential buffer
- Dual 1:6 differential
buffer
- Dual 1:8 differential buffer
- Supply voltage: 1.71V to 3.465V
- Dual
output common mode voltage operation:
- Output common mode voltage: 0.7V at
1.8V supply voltage.
- Output common mode voltage: 1.2V at
2.5V/3.3V supply voltage
- Low additive jitter:
- < 17fs RMS typical in 12kHz to
20MHz at
1250.25MHz
- < 22fs RMS typical in 12kHz to
20MHz at 625MHz
- < 60fs RMS maximum in 12kHz to
20MHz at 156.25MHz
- Very low phase noise
floor: -164dBc/Hz (typical at 156.25MHz)
- Very low propagation delay: < 575ps
maximum
- Output skew:
- 15ps maximum (LMK1D2102, LMK1D2104)
- 20ps maximum (LMK1D2106, LMK1D2106)
- Part to Part skew: 150ps
- High-swing LVDS (boosted mode): 500mV VOD typical
when AMP_SELA, AMP_SELB= Floating
- Bank enable/disable using AMP_SELA and AMP_SELB
Section 8.4.1
- Fail-safe input operation
- Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
- LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
- Extended industrial temperature range: –40°C to
105°C
