LMK1D210x Low Additive Jitter LVDS Buffer

1 Features

High-performance LVDS clock buffer family: up to 2 GHz
- Dual 1:6 differential buffer
- Dual 1:8 differential buffer
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12-kHz to
20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
Bank enable/disable using the EN pin
Fail-safe input operation
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, V_{AC_REF}, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
- LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)
- LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)