LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)
LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)
The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.
The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).
Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
PART NUMBER(1) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMK1D2106 | VQFN (40) | 6.00 mm × 6.00 mm |
LMK1D2108 | VQFN (48) | 7.00 mm × 7.00 mm |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | LMK1D2106 | LMK1D2108 | ||
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT | ||||
IN0_P, IN0_N | 8, 9 | 9, 10 | I | Primary: Differential input pair or single-ended input |
IN1_P, IN1_N | 2, 3 | 3, 4 | I | Secondary: Differential input pair or single-ended input |
Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N. | ||||
BANK ENABLE | ||||
EN | 1 | 2 | I | Output bank enable/disable with an internal 500-kΩ pullup and 320-kΩ pulldown. See Table 8-2. |
AMPLITUDE SELECT | ||||
AMP_SEL | 10 | 11 | I | Output amplitude swing select with an internal 500-kΩ pullup and 320-kΩ pulldown. See Table 8-3. |
BIAS VOLTAGE OUTPUT | ||||
VAC_REF0,VAC_REF1 | 7, 4 | 8, 5 | O | Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin. |
DIFFERENTIAL CLOCK OUTPUT | ||||
OUT0_P, OUT0_N | 12, 13 | 14, 15 | O | Differential LVDS output pair number 0 |
OUT1_P, OUT1_N | 14, 15 | 16, 17 | O | Differential LVDS output pair number 1 |
OUT2_P, OUT2_N | 16, 17 | 18, 19 | O | Differential LVDS output pair number 2 |
OUT3_P, OUT3_N | 18, 19 | 20, 21 | O | Differential LVDS output pair number 3 |
OUT4_P, OUT4_N | 22, 23 | 22, 23 | O | Differential LVDS output pair number 4 |
OUT5_P, OUT5_N | 24, 25 | 25, 26 | O | Differential LVDS output pair number 5 |
OUT6_P, OUT6_N | 26, 27 | 27, 28 | O | Differential LVDS output pair number 6 |
OUT7_P, OUT7_N | 28, 29 | 29, 30 | O | Differential LVDS output pair number 7 |
OUT8_P, OUT8_N | 32, 33 | 31, 32 | O | Differential LVDS output pair number 8 |
OUT9_P, OUT9_N | 34, 35 | 33, 34 | O | Differential LVDS output pair number 9 |
OUT10_P, OUT10_N | 36, 37 | 35, 36 | O | Differential LVDS output pair number 10 |
OUT11_P, OUT11_N | 38, 39 | 38, 39 | O | Differential LVDS output pair number 11 |
OUT12_P, OUT12_N | — | 40, 41 | O | Differential LVDS output pair number 12 |
OUT13_P, OUT13_N | — | 42, 43 | O | Differential LVDS output pair number 13 |
OUT14_P, OUT14_N | — | 44, 45 | O | Differential LVDS output pair number 14 |
OUT15_P, OUT15_N | — | 46, 47 | O | Differential LVDS output pair number 15 |
SUPPLY VOLTAGE | ||||
VDDA | 6, 11, 20 | 7, 13, 24 | P | Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 0 |
VDDB | 5, 31, 40 | 6, 37, 48 | P | Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 1 |
GROUND | ||||
GND | 21, 30 | 1, 12 | G | Ground |
MISC | ||||
DAP | DAP | DAP | G | Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Supply voltage | –0.3 | 3.6 | V |
VIN | Input voltage | –0.3 | 3.6 | V |
VO | Output voltage | –0.3 | VDD + 0.3 | V |
IIN | Input current | –20 | 20 | mA |
IO | Continuous output current | –50 | 50 | mA |
TJ | Junction temperature | 135 | °C | |
Tstg | Storage temperature (2) | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±3000 | V |
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | ±1000 |