SNAS829A October   2021  – January 2022 LMK1D2106 , LMK1D2108

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

Device Information
PART NUMBER(1)PACKAGEBODY SIZE (NOM)
LMK1D2106VQFN (40)6.00 mm × 6.00 mm
LMK1D2108VQFN (48)7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
Application Example