SNAS880 December 2024 LMK3C0105
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Consider a typical Gigabit Ethernet Switch application. In a system such as this, the clocks are expected to be available upon request without the need for any additional device-level programming. The default device configuration outputs five 25MHz LVCMOS clocks, all enabled by default. A typical output clock requirement in this application is two 25MHz LVCMOS clocks for the PHY, and both a 25MHz and 100MHz LVCMOS clock for the FPGA. The section below describes the detailed design procedure to generate the required output frequencies for the above scenario using the LMK3C0105.