SNAS880 December   2024 LMK3C0105

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Digital State Machine
        3. 7.4.2.3 Spread-Spectrum Clocking
        4. 7.4.2.4 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
        2. 7.4.3.2 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Separate Output Enable
        4. 7.4.4.4 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1804]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA7]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x5D1F]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3000/0x1000]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 8.1.14 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RER|16
Thermal pad, mechanical data (Package|Pins)

4 Pin Configuration and Functions

LMK3C0105 LMK3C0105 16-Pin TQFN Top View Figure 4-1 LMK3C0105 16-Pin TQFN Top View
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
OUTA, OUTB, OUTC, OUTD8, 7, 12, 11OLVCMOS clock outputs. Supports 1.8V/2.5V/3.3V LVCMOS.
REF_CTRL (OUTE)15I/O

Multifunctional pin. At power-up, the state of this pin is latched to select the functionality of Pin 2, Pin 3 and Pin 4. Pull low for I2C mode or high for OTP mode prior to power-up. After power-up, this pin can be programmed as an additional LVCMOS output (OUTE), active-high CLK_READY signal (default), or disabled.

See REF_CTRL Operation for more details.

This pin has an 880kΩ internal pull-down resistor.

OE1I

Global Output Enable. Active low. 2-state logic input pin.

This pin has a 75kΩ internal pull-down resistor.

See Output Enable for more details.

  • Low: Outputs are enabled
  • High: Outputs are disabled
I2C_ADDR2I

This pin, in I2C Mode, can be used to set the I2C address from one of four options at power-up. See I2C Mode for more details.

This pin has a 75kΩ internal pull-down resistor.

  • I2C Mode: This pin selects the I2C address.
OTP_SEL0/SCL, OTP_SEL1/SDA3, 4I, I/OMultifunctional pin. Functionality is determined by REF_CTRL (pin 15) at power-up. See OTP Mode and I2C Mode for details.
  • I2C Mode: These pins are the I2C clock and data connections.
  • OTP Mode: These pins select the OTP page.
VDD5, 14, 16P1.8V, 2.5V or 3.3V device power supply. A 0.1µF capacitor must be placed as close to each of the pins as possible.
VDDO_010P1.8V, 2.5V or 3.3V OUTA and OUTB power supply. If VDD is 1.8V or 2.5V, the VDDO pins must be the same voltage as VDD. A 0.1µF capacitor must be placed as close to the pin as possible.
VDDO_1 13 P 1.8V, 2.5V or 3.3V OUTC and OUTD power supply. If VDD is 1.8V or 2.5V, the VDDO pins must be the same voltage as VDD. A 0.1µF capacitor must be placed as close to the pin as possible.
NC6, 9N/A

No connect. Pins can be connected to GND, VDD, or otherwise tied to any potential within the Supply Voltage range stated in the Absolute Maximum Ratings.

DAP17GGND
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.