SNAS880 December   2024 LMK3C0105

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Digital State Machine
        3. 7.4.2.3 Spread-Spectrum Clocking
        4. 7.4.2.4 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
        2. 7.4.3.2 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Separate Output Enable
        4. 7.4.4.4 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1804]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA7]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x5D1F]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3000/0x1000]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 8.1.14 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RER|16
Thermal pad, mechanical data (Package|Pins)

9.2.3 Detailed Design Procedure

Design of all aspects of the LMK3C0105 is straightforward, and software support is available to assist in frequency planning and part programming. This design procedure gives a straightforward outline of the process.

  1. Frequency Planning
    1. The first step of designing an LMK3C0105 configuration is to determine the FOD frequencies that are required to generate the required output frequencies. The process is as such:
      1. If both output frequencies are the same, and have the same SSC settings (that is, both use SSC or both do not use SSC), only one FOD is required.
      2. If both output frequencies are different, but have the same SSC settings, the outputs can share an FOD to conserve current. If both frequencies can be generated from dividing a single valid FOD frequency by the channel divider options, then the second FOD can be disabled. Otherwise, both FODs must be used. If both outputs require SSC, then this frequency plan cannot be supported by the LMK3C0105 device.
      3. If one output requires SSC and the other does not, then the SSC output must use FOD0 and the non-SSC output must use FOD1.
    2. If SSC is being used, determine whether or not a preconfigured down-spread modulation, a custom down-spread modulation, or a center-spread modulation is required for the application. If a custom configuration is required, follow the steps outlined in Section 7.4.2.3.
    3. Set the digital clock divider such that the digital clock frequency is as close to 50MHz as possible.
    4. Determine the REF_CTRL pin functionality. If this is used as an additional LVCMOS reference clock, verify that the desired frequency can be generated based on the FOD0 and FOD1 frequencies, as the divider range for the REF_CLK output is /2, /4, or /8 only.
      1. Keep in mind that if SSC is used on FOD0, and the REF_CLK source is FOD0, this output now has SSC as well.
  2. Setting the Output Formats
    1. The output formats that are required are based upon the number of clocks needed in the system. For crystal replacement, this is most often a collection of 24MHz, 25MHz, 27MHz, or 50MHz LVCMOS clocks.
    2. OUTA and OUTB, or OUTC and OUTD, can be in phase, opposite, or individually enabled or disabled. OUTA and OUTC are always in phase. This allows for the generation of up to five LVCMOS clocks at a time, up to four of which can be in phase.
      1. For LVCMOS outputs, the VDDO_x voltage MUST match the VDD voltage if VDD is 1.8V or 2.5V.
  3. Output Enable Behavior
    1. The output enable pin is active low by default, with an internal pulldown resistor to GND. If this functionality is not desired, then OE_PIN_POLARITY can be set to '0' to change the behavior of the OE pin to active-high. If this is done, the internal pulldown is disabled, and an internal pullup to VDD is used.
    2. Determine whether or not both outputs being disabled means that the device enters low-power mode. While this is able to conserve current, low-power mode is not recommended for any applications where the clocks must turn back on quickly, such as PCIe clocking.

For the 10GB PHY, the following settings are required:

  1. One FOD can be used to generate all outputs. As such, FOD0 can be set to have an output frequency of 200MHz, with Channel Divider 0 set to divide by 8. Often, if two clocks of the same frequency are required by a single device, these clocks need to be in phase. Both output drivers select Channel Divider 0. Output Driver 0 is set for LVCMOS in-phase, and Output Driver 1 is set for LVCMOS OUTD only. When configured for OUTD only, OUTD is in phase with OUTA.
    1. DIG_CLK_N_DIV must be set to two to set the state machine clock properly. The state machine clock must be as close to 50MHz as possible without exceeding this frequency. In this case, DIG_CLK_N_DIV is set to 2 for a total divide of 4. Equation 9 shows the relationship between the digital state machine frequency, the frequency selected by the CH0_FOD_SEL multiplexer, and the DIG_CLK_N_DIV field. Write the DIG_CLK_N_DIV field only while the device is in the low power state.
  2. The REF_CTRL pin is used for generating the 100MHz LVCMOS clock. Set REF_CLK_FOD_SEL to 0 for selecting FOD0 as the REF_CTRL clock source. REF_CLK_DIV must be set to 1 for a divide by 2 from FOD0. Set REF_CTRL_PIN_FUNC to 2 for setting the REF_CTRL pin as an output clock.
Equation 9. FDIG = FCH0_FOD_SEL2 + DIG_CLK_N_DIV 

where FDIG is the digital state machine clock frequency and FCH0_FOD_SEL is the frequency selected by the CHO_FOD_SEL multiplexer