SNAS880 December 2024 LMK3C0105
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
FREQUENCY STABILITY | ||||||
∆ftotal | Total frequency stability | All factors included: temperature variation, 10-year aging, solder shift, hysteresis and initial frequency accuracy | –25 | 25 | ppm | |
LVCMOS CLOCK OUTPUT CHARACTERISTICS | ||||||
fout | Output frequency | 2.5 | 200 | MHz | ||
dV/dt | Output slew rate | VDDO = 3.3V ± 5%, measured from 20% to 80%, 4.7pF load | 2.6 | 4.7 | V/ns | |
VDDO = 2.5V ± 5%, measured from 20% to 80%, 4.7pF load | 2.6 | 3.7 | V/ns | |||
VDDO = 1.8V ± 5%, measured from 20% to 80%, 4.7pF load | 1.5 | 3.2 | V/ns | |||
VOH | Output high voltage | IOH = –15mA at 3.3V | 0.8 x VDDO | VDDO | V | |
IOH = –12mA at 2.5V | ||||||
IOH = –8mA at 1.8V | ||||||
VOL | Output low voltage | IOL = 15mA at 3.3V | 0.4 | V | ||
IOL = 12mA at 2.5V | ||||||
IOL = 8mA at 1.8V | ||||||
Ileak | Output leakage current | Output tri-stated. VDD = VDDO = 3.465V | –5 | 0 | 5 | µA |
Rout | Output impedance | 17 | Ω | |||
ODC | Output duty cycle | fout ≤ 156.25MHz | 45 | 55 | % | |
fout > 156.25MHz | 40 | 60 | % | |||
tskew | Output-to-output skew | Same FOD, LVCMOS output | 50 | ps | ||
Cload | Maximum load capacitance | 15 | pF | |||
LVCMOS REFCLK CHARATERISTICS | ||||||
fout | Output frequency | See(1) | 12.5(2) | 200 | MHz | |
dV/dt | Output slew rate | VDDO = 3.3V ± 5%, measured from 20% to 80%, 4.7pF load(1) | 2.6 | 6.7 | V/ns | |
VDDO = 2.5V ± 5%, measured from 20% to 80%, 4.7pF load(1)(3) | 1.8 | 4.5 | V/ns | |||
VDDO = 1.8V ± 5%, measured from 20% to 80%, 4.7pF load(1)(3) | 1 | 3.2 | V/ns | |||
Ileak | Output leakage current | Output tri-stated. VDD = VDDO = 3.465V(1)(3) | –5 | 5 | µA | |
Rout | Output impedance | 17 | Ω | |||
ODC | Output duty cycle | fout ≤ 156.25MHz(1) | 45 | 55 | % | |
ODC | Output duty cycle | fout > 156.25MHz(1) | 40 | 60 | % | |
Cload | Maximum load capacitance | See(1) | 15 | pF | ||
RJ | Random jitter | 12kHz to 20MHz integrated jitter at 50MHz(1) | 0.5 | ps | ||
SSC CHARACTERISTICS | ||||||
fout | Output frequency range that supports SSC (any output format) | 2.5 | 200 | MHz | ||
fSSC | SSC modulation frequency | 30 | 31.5 | 33 | kHz | |
fSSC-deviation | SSC deviation (modulation depth) | Down spread (programmable) | –3 | –0.1 | % | |
Center spread (programmable) | ±0.05 | ±1.5 | % | |||
fSSC-deviation-accuracy | SSC deviation accuracy | fout ≤ 100MHz, down spread | 0 | 0.01 | % | |
100MHz < fout ≤ 200MHz, down spread | 0 | 0.05 | % | |||
fout ≤ 100MHz, center spread | 0 | 0.01 | % | |||
100MHz < fout ≤ 200MHz, center spread | 0 | 0.05 | % | |||
df/dt | max SSC frequency slew rate | 0 < fSSC-deviation ≤ –0.5% | 1250 | ppm/µs | ||
TIMING CHARACTERISTICS | ||||||
tstartup | Start-up time | VDD = 2.5V or 3.3V. Time elapsed from all VDD pins reach 2.1V until first output clock rising edge. Output clock is always within specification | 1 | ms | ||
VDD = 1.8V. Time elapsed from all VDD pins reach 1.6V until first output clock rising edge. Output clock is always within specification | 1.5 | ms | ||||
tOE | Output enable time. | After CLOCK_READY status is '1', time elapsed between OE assertion and first output clock rising edge. Output is not tristated when disabled. | 7 | output clock cycles | ||
tOD | Output disable time. | Time elapsed between OE deassertion and last output clock falling edge. | 7 | output clock cycles | ||
POWER CONSUMPTION CHARACTERISTICS | ||||||
IDD | Core supply current, not including output drivers | One FOD enabled, 100MHz ≤ fFOD ≤ 200MHz | 57.5 | 79.9 | mA | |
One FOD enabled, 200MHz < fFOD ≤ 400MHz | 67 | 90.7 | mA | |||
Two FODs enabled, 100MHz ≤ fFOD ≤ 200MHz | 81.1 | 105.8 | mA | |||
Two FODs enabled, 200MHz < fFOD ≤ 400MHz | 97.8 | 125.8 | mA | |||
IDDO | Output supply current, per output channel | 1.8V LVCMOS. fout = 50MHz | 4.2 | 5 | mA | |
1.8V LVCMOS. fout = 200MHz | 11.7 | 13.4 | mA | |||
2.5V LVCMOS. fout = 50MHz | 5.6 | 6.4 | mA | |||
2.5V LVCMOS. fout = 200MHz | 15.3 | 17.3 | mA | |||
3.3V LVCMOS. fout = 50MHz | 6.8 | 7.7 | mA | |||
3.3V LVCMOS. fout = 200MHz | 19.2 | 21.7 | mA | |||
IDDREF | REFCLK supply current | 1.8V LVCMOS. fout = 50MHz | 3.4 | 3.9 | mA | |
1.8V LVCMOS. fout = 200MHz | 9.5 | 11.7 | mA | |||
2.5V LVCMOS. fout = 50MHz | 4.7 | 5.3 | mA | |||
2.5V LVCMOS. fout = 200MHz | 12.8 | 15.8 | mA | |||
3.3V LVCMOS. fout = 50MHz | 5.9 | 6.6 | mA | |||
3.3V LVCMOS. fout = 200MHz | 16.6 | 20.2 | mA | |||
PSNR CHARACTERISTICS | ||||||
PSNRLVCMOS | Power Supply Noise Rejection for LVCMOS outputs(3) | 10kHz | –76.7 | -58.1 | dBc | |
50kHz | –80.9 | -57.9 | dBc | |||
100kHz | –81.8 | -57 | dBc | |||
500kHz | –84.3 | -61.7 | dBc | |||
1MHz | –97.6 | -78.1 | dBc | |||
5MHz | –104.3 | -79 | dBc | |||
10MHz | –108.7 | -89.5 | dBc | |||
2-STATE LOGIC INPUT CHARACTERISTICS | ||||||
VIH-Pin2 | Input high voltage for Pin 2 | 0.7 × VDD | VDD + 0.3 | V | ||
VIL-Pin2 | Input low voltage for Pin 2 | GND – 0.3 | 0.3 × VDD | V | ||
VIH-Pin1 | Input high voltage for Pin 1 | 1.15 | VDD + 0.3 | V | ||
VIL-Pin1 | Input low voltage for Pin 1 | –0.3 | 0.65 | V | ||
VIH-Pin3,4 | Input voltage high for OTP_SEL[1:0] | 0.7 × VDD | VDD + 0.3 | V | ||
VIL-Pin3,4 | Input voltage low for OTP_SEL[1:0] | GND - 0.3 | 0.8 | V | ||
VIH-Pin15 | Input voltage high for Pin 15 | 0.65 × VDD | VDD + 0.3 | V | ||
VIL-Pin15 | Input voltage low for Pin 15 | –0.3 | 0.4 | V | ||
Rext-up/down-Pin1,2 | Recommended external pullup or pulldown resistor for Pin 1, 2 | 0 | 1 | 10 | kΩ | |
Rext-up/down-Pin3,4,15 | Recommended external pullup or pulldown resistor for Pin 3, 4, 15 | 0 | 10 | 60 | kΩ | |
tR/tF | OE signal rise or fall time | 10 | ns | |||
Cin | Input capacitance | 3 | pF |