SNAS835 September   2022 LMK5B33414

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
    2. 7.2 Output Clock Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 PLL Architecture Overview
      2. 8.2.2 DPLL
        1. 8.2.2.1 Independent DPLL Operation
        2. 8.2.2.2 Cascaded DPLL Operation
        3. 8.2.2.3 APLL Cascaded With DPLL
      3. 8.2.3 APLL-Only Mode
    3. 8.3 Feature Description
      1. 8.3.1  Oscillator Input (XO)
      2. 8.3.2  Reference Inputs
      3. 8.3.3  Clock Input Interfacing and Termination
      4. 8.3.4  Reference Input Mux Selection
        1. 8.3.4.1 Automatic Input Selection
        2. 8.3.4.2 Manual Input Selection
      5. 8.3.5  Hitless Switching
        1. 8.3.5.1 Hitless Switching With Phase Cancellation
        2. 8.3.5.2 Hitless Switching With Phase Slew Control
        3. 8.3.5.3 Hitless Switching With 1-PPS Inputs
      6. 8.3.6  Gapped Clock Support on Reference Inputs
      7. 8.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 8.3.7.1 XO Input Monitoring
        2. 8.3.7.2 Reference Input Monitoring
          1. 8.3.7.2.1 Reference Validation Timer
          2. 8.3.7.2.2 Frequency Monitoring
          3. 8.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 8.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 8.3.7.2.5 Phase Valid Monitor for 1-PPS Inputs
        3. 8.3.7.3 PLL Lock Detectors
        4. 8.3.7.4 Tuning Word History
        5. 8.3.7.5 Status Outputs
        6. 8.3.7.6 Interrupt
      8. 8.3.8  PLL Relationships
        1. 8.3.8.1  PLL Frequency Relationships
          1. 8.3.8.1.1 APLL Phase Detector Frequency
          2. 8.3.8.1.2 APLL VCO Frequency
          3. 8.3.8.1.3 DPLL TDC Frequency
          4. 8.3.8.1.4 DPLL VCO Frequency
          5. 8.3.8.1.5 Clock Output Frequency
        2. 8.3.8.2  Analog PLLs (APLL1, APLL2, APLL3)
        3. 8.3.8.3  APLL Reference Paths
          1. 8.3.8.3.1 APLL XO Doubler
          2. 8.3.8.3.2 APLL XO Reference (R) Divider
        4. 8.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 8.3.8.5  APLL Feedback Divider Paths
          1. 8.3.8.5.1 APLL N Divider With SDM
        6. 8.3.8.6  APLL Loop Filters (LF1, LF2, LF3)
        7. 8.3.8.7  APLL Voltage-Controlled Oscillators (VCO1, VCO2, VCO3)
          1. 8.3.8.7.1 VCO Calibration
        8. 8.3.8.8  APLL VCO Clock Distribution Paths
        9. 8.3.8.9  DPLL Reference (R) Divider Paths
        10. 8.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 8.3.8.11 DPLL Loop Filter (DLF)
        12. 8.3.8.12 DPLL Feedback (FB) Divider Path
      9. 8.3.9  Output Clock Distribution
      10. 8.3.10 Output Channel Muxes
      11. 8.3.11 Output Dividers (OD)
      12. 8.3.12 SYSREF/1-PPS
      13. 8.3.13 Output Delay
      14. 8.3.14 Clock Outputs (OUTx_P/N)
        1. 8.3.14.1 Differential Output
        2. 8.3.14.2 LVCMOS Output
        3. 8.3.14.3 SYSREF/1-PPS Output Replication
        4. 8.3.14.4 Output Auto-Mute During LOL
      15. 8.3.15 Glitchless Output Clock Start-Up
      16. 8.3.16 Clock Output Interfacing and Termination
      17. 8.3.17 Output Synchronization (SYNC)
      18. 8.3.18 Zero-Delay Mode (ZDM)
      19. 8.3.19 Time Elapsed Counter (TEC)
        1. 8.3.19.1 Configuring TEC Functionality
        2. 8.3.19.2 SPI as a Trigger Source
        3. 8.3.19.3 GPIO Pin as a TEC Trigger Source
          1. 8.3.19.3.1 An Example: Making a Time Elapsed Measurement Using TEC and GPIO1 as Trigger
        4. 8.3.19.4 TEC Timing
        5. 8.3.19.5 Other TEC Behavior
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Start-Up
        1. 8.4.1.1 ROM Selection
        2. 8.4.1.2 EEPROM Overlay
      2. 8.4.2 DPLL Operating States
        1. 8.4.2.1 Free-Run
        2. 8.4.2.2 Lock Acquisition
        3. 8.4.2.3 DPLL Locked
        4. 8.4.2.4 Holdover
      3. 8.4.3 PLL Start-Up Sequence
      4. 8.4.4 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 8.4.4.1 DPLL DCO Control
          1. 8.4.4.1.1 DPLL DCO Relative Adjustment Frequency Step Size
          2. 8.4.4.1.2 APLL DCO Frequency Step Size
      5. 8.4.5 APLL Frequency Control
      6. 8.4.6 Zero-Delay Mode Synchronization
      7. 8.4.7 DPLL Programmable Phase Delay
    5. 8.5 Programming
      1. 8.5.1 Interface and Control
      2. 8.5.2 I2C Serial Interface
        1. 8.5.2.1 I2C Block Register Transfers
      3. 8.5.3 SPI Serial Interface
        1. 8.5.3.1 SPI Block Register Transfer
      4. 8.5.4 Register Map Generation
      5. 8.5.5 General Register Programming Sequence
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Start-Up Sequence
      2. 9.1.2 Power Down (PD#) Pin
      3. 9.1.3 Strap Pins for Start-Up
      4. 9.1.4 Pin States
      5. 9.1.5 ROM and EEPROM
      6. 9.1.6 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 9.1.6.1 Power-On Reset (POR) Circuit
        2. 9.1.6.2 Powering Up From a Single-Supply Rail
        3. 9.1.6.3 Power Up From Split-Supply Rails
        4. 9.1.6.4 Non-Monotonic or Slow Power-Up Supply Ramp
      7. 9.1.7 Slow or Delayed XO Start-Up
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Supply Bypassing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Reliability
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Clock Tree Architect Programming Software
        2. 10.1.1.2 Texas Instruments Clocks and Synthesizers (TICS) Pro Software
        3. 10.1.1.3 PLLatinum™ Simulation Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Glossary
    7. 10.7 Electrostatic Discharge Caution
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 LMK5B33414 RGC Package 64-Pin VQFN Top View
Table 5-1 LMK5B33414 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
POWER
VDDO_0_11PPower supply for OUT0 and OUT1
VDD_APLL1_XO8PPower supply for XO and APLL1
VDDO_2_311PPower supply for OUT2 and OUT3
VDD_APLL223PPower supply for APLL2
VDDO_4_TO_728PPower supply for OUT4 to OUT7
VDD_IN033PPower supply for IN0 DPLL reference
VDD_IN137PPower supply for IN1 DPLL reference
VDD_DIG41PPower supply for digital
VDD_IN2344PPower supply for IN2 and IN3 reference inputs
VDD_APLL347PPower supply for APLL3
VDDO_8_TO_1355PPower supply for OUT8 to OUT13
DAPN/AGGround
CORE BLOCKS(2)
LF16AExternal loop filter cap for APLL1 (100 nF)
CAP_APLL17ALDO bypass capacitor for APLL1 VCO (10 µF)
LF219AExternal loop filter cap for APLL2 (100 nF)
CAP3_APLL220AInternal bias bypass capacitor for APLL2 VCO (10 µF)
CAP2_APLL221AInternal bias bypass capacitor for APLL2 VCO (10 µF)
CAP1_APLL222ALDO bypass capacitor for APLL2 VCO (10 µF)
CAP_DIG40ALDO bypass capacitor for Digital Core Logic (100 nF)
CAP_APLL348AInternal bias bypass capacitor for APLL3 (10 µF)
LF349AExternal loop filter cap for APLL3 (470 nF)
INPUT BLOCKS
XO9IXO/TCXO/OCXO input pin
IN0_P34IFirst input reference to DPLLx or buffered to OUT0 or OUT1
IN0_N35I
IN1_N38ISecond input reference to DPLLx or buffered to OUT0 or OUT1
IN1_P39I
IN2_P42IThird input reference to DPLLx or buffered to OUT0 or OUT1.
IN2_N43I
IN3_N45IFourth input reference to DPLLx or buffered to OUT0 or OUT1
IN3_P46I
OUTPUT BLOCKS
OUT0_P2OClock Output 0. Sources from all DPLL references, XO, all VCO post-dividers. Supports 1-PPS output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL, 1.8-V LVCMOS, or 2.65-V LVCMOS.
OUT0_N3O
OUT1_N4OClock Output 1. Sources from all DPLL references, XO, all VCO post-dividers. Supports 1-PPS output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL, 1.8-V LVCMOS, or 2.65-V LVCMOS.
OUT1_P5O
OUT2_P12OClock Output 2. Sources from APLL1, APLL2 and APLL3. No 1-PPS output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT2_N13O
OUT3_N14OClock Output 3. Sources from same output mux as OUT2 from APLL1, APLL2 or APLL3. No 1-PPS output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL
OUT3_P15O
OUT5_P24OClock Output 5. Sources from APLL2 and APLL3.Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT5_N25O
OUT4_N26OClock Output 4. Sources from APLL2 and APLL3. Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT4_P27O
OUT6_P29OClock Output 6. Sources from APLL2 and APLL3. Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT6_N30O
OUT7_N31OClock Output 7. Sources from APLL2 and APLL3. Supports 1-PPS output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT7_P32O
OUT8_P51OClock Output 8. Sources from APLL2 and APLL3. Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT8_N52O
OUT9_N53OClock Output 9. Sources from APLL2 and APLL3. Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT9_P54O
OUT10_P56OClock Output 10. Sources from APLL2 and APLL3. Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL
OUT10_N57O
OUT11_N58OClock Output 11. Sources from APLL2 and APLL3. Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT11_P59O
OUT12_P60OClock Output 12. Sources from APLL2 and APLL3. Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT12_N61O
OUT13_N62OClock Output 13. Sources from APLL2 and APLL3. Capable of supporting 1-PPS or SYSREF output. Programmable formats: AC-LVPECL, HSDS, LVDS, HCSL.
OUT13_P63O
LOGIC CONTROL/STATUS
GPIO2(3)10I/O, SPOR: ROM page select
Normal Operation: GPIO input or output (see description)
SDIO(4)16I/OSPI or I2C Data (SDA)
SCK(4)17ISPI or I2C Clock (SCL)
SCS_ADD(3)18I, SSPI Chip Select (2-state) or POR: I2C address select, LSB (3-state)
PD# 36IDevice power down (Active low), internal 200-kΩ pullup to VCC
GPIO0(3)50I/O, SPOR: ROM page select
Normal Operation: GPIO input or output (see description)
GPIO1(3)64I/O, SPOR: I2C or SPI select
Normal Operation: GPIO input or output (see description)
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input or Output, A = Analog, S = Configuration.
(2) Do not apply external stimulus to core pins. These performance critical pins are not designed to meet normal latch up testing compliance levels. For best filtering performance, capacitors should be placed close to the IC.
(3) When 3 level mode is enabled during power supply ramp or when PD# is LOW: internal voltage divider of 555 kΩ to VCC and 201 kΩ to GND. When 2 level input mode is enabled: internal 408-kΩ pulldown to GND.
(4) 670-kΩ pullup to internal 2.6-V LDO.