SNAS750B November 2020 – March 2021 LMK5C33216
PRODUCTION DATA
The XO input has a coarse frequency monitor to help qualify the input before it is used to lock the APLLs.
The XO frequency detector clears its LOS_FDET_XO flag when the input frequency is detected within the supported range of 10 MHz to 100 MHz. The XO frequency monitor uses a RC-based detector and cannot precisely detect if the XO input clock has sufficient frequency stability to ensure successful VCO calibration during the PLL start-up when the external XO clock has a slow or delayed start-up behavior. See Section 10.1.6 for more information.
The XO frequency detector can be bypassed by setting the XO_FDET_BYP bit (shown as EN in Figure 9-17) so that the XO input is always considered valid by the PLL control state machine. The user can observe the LOS_FDET_XO status flag through the status pins and status bit. Setting XO_FDET_BYP bit will bypass the detect, but will not reflect any change to LOS_FDET_XO status flag.