SNAS750B November 2020 – March 2021 LMK5C33216
PRODUCTION DATA
The LVCMOS driver has two outputs per pair. Each output on P and N can be configured for normal polarity, inverted polarity, or disabled as Hi-Z or static low level. The LVCMOS output high level (VOH) is determined by the internal programmable LDO regulator voltage of 1.8 V or 2.65 V for rail-to-rail LVCMOS output voltage swing. LVCMOS mode is only supported on channel outputs 0 and 1 and is primarily there to support ASIC or processor clock which don’t require stringent phase noise floor requirements.
Because an LVCMOS output clock is an unbalanced signal with large voltage swing, it can be a strong aggressor and couple noise onto other jitter-sensitive differential output clocks. If an LVCMOS clock is required from an output pair, configure the pair with both outputs enabled but with opposite polarity (+/– or –/+) and leave the unused output floating with no trace connected.