SNAS750B November 2020 – March 2021 LMK5C33216
PRODUCTION DATA
To support IEEE 1588 and other clock steering applications, the DPLL supports DCO mode to allow precise output clock frequency adjustment of less than 0.001 ppb/step. DCO may be implemented using DPLL DCO control or APLL DCO control. While the DPLL is operating in closed loop mode, DPLL DCO modifies the effective DPLL numerator. While the DPLL is in holdover or not used, APLL DCO adjusts the effective APLL numerator.