SNAS750B November   2020  – March 2021 LMK5C33216

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
    2. 8.2 Output Clock Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
      1. 9.2.1 PLL Architecture Overview
      2. 9.2.2 DPLL
        1. 9.2.2.1 Independent DPLL Operation
        2. 9.2.2.2 Cascaded DPLL Operation
        3. 9.2.2.3 APLL Cascaded with DPLL
      3. 9.2.3 APLL-Only Mode
    3. 9.3 Feature Description
      1. 9.3.1  Oscillator Input (XO)
      2. 9.3.2  Reference Inputs
      3. 9.3.3  Clock Input Interfacing and Termination
      4. 9.3.4  Reference Input Mux Selection
        1. 9.3.4.1 Automatic Input Selection
        2. 9.3.4.2 Manual Input Selection
      5. 9.3.5  Hitless Switching
        1. 9.3.5.1 Hitless Switching with Phase Cancellation
        2. 9.3.5.2 Hitless Switching With Phase Slew Control
        3. 9.3.5.3 Hitless Switching With 1-PPS Inputs
      6. 9.3.6  Gapped Clock Support on Reference Inputs
      7. 9.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 9.3.7.1 XO Input Monitoring
        2. 9.3.7.2 Reference Input Monitoring
          1. 9.3.7.2.1 Reference Validation Timer
          2. 9.3.7.2.2 Frequency Monitoring
          3. 9.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 9.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 9.3.7.2.5 Phase Valid Monitor for 1-PPS Inputs
        3. 9.3.7.3 PLL Lock Detectors
        4. 9.3.7.4 Tuning Word History
        5. 9.3.7.5 Status Outputs
        6. 9.3.7.6 Interrupt
      8. 9.3.8  PLL Relationships
        1. 9.3.8.1  PLL Frequency Relationships
          1. 9.3.8.1.1 APLL Phase Detector Frequency
          2. 9.3.8.1.2 APLL VCO Frequency
          3. 9.3.8.1.3 DPLL TDC Frequency
          4. 9.3.8.1.4 DPLL VCO Frequency
          5. 9.3.8.1.5 Clock Output Frequency
        2. 9.3.8.2  Analog PLLs (APLL1, APLL2, APLL3)
        3. 9.3.8.3  APLL Reference Paths
          1. 9.3.8.3.1 APLL XO Doubler
          2. 9.3.8.3.2 APLL XO Reference (R) Divider
        4. 9.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 9.3.8.5  APLL Feedback Divider Paths
          1. 9.3.8.5.1 APLL N Divider with SDM
        6. 9.3.8.6  APLL Loop Filters (LF1, LF2, LF3)
        7. 9.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2, VCO3)
          1. 9.3.8.7.1 VCO Calibration
        8. 9.3.8.8  APLL VCO Clock Distribution Paths
        9. 9.3.8.9  DPLL Reference (R) Divider Paths
        10. 9.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 9.3.8.11 DPLL Loop Filter (DLF)
        12. 9.3.8.12 DPLL Feedback (FB) Divider Path
      9. 9.3.9  Output Clock Distribution
      10. 9.3.10 Output Channel Muxes
      11. 9.3.11 Output Dividers (OD)
      12. 9.3.12 SYSREF
      13. 9.3.13 Output Delay
      14. 9.3.14 Clock Outputs (OUTx_P/N)
        1. 9.3.14.1 Differential Output
        2. 9.3.14.2 LVCMOS Output
        3. 9.3.14.3 Output Auto-Mute During LOL
      15. 9.3.15 Glitchless Output Clock Start-Up
      16. 9.3.16 Clock Output Interfacing and Termination
      17. 9.3.17 Output Synchronization (SYNC)
      18. 9.3.18 Zero-Delay Mode (ZDM) Synchronization
      19. 9.3.19 Time of Day (ToD) Counter
        1. 9.3.19.1 Configuring ToD Functionality
        2. 9.3.19.2 SPI as a Trigger Source
        3. 9.3.19.3 GPIO Pin as a ToD Trigger Source
          1. 9.3.19.3.1 An Example: Making a time measurement using ToD and GPIO1 as trigger
        4. 9.3.19.4 ToD Timing
        5. 9.3.19.5 Other ToD Behavior
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Start-Up
        1. 9.4.1.1 ROM Selection
        2. 9.4.1.2 EEPROM Overlay
      2. 9.4.2 DPLL Operating States
        1. 9.4.2.1 Free-Run
        2. 9.4.2.2 Lock Acquisition
        3. 9.4.2.3 DPLL Locked
        4. 9.4.2.4 Holdover
      3. 9.4.3 PLL Start-Up Sequence
      4. 9.4.4 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 9.4.4.1 DPLL DCO Control
          1. 9.4.4.1.1 DPLL DCO Relative Adjustment Frequency Step Size
          2. 9.4.4.1.2 APLL DCO Frequency Step Size
      5. 9.4.5 APLL Frequency Control
      6. 9.4.6 Zero-Delay Mode Synchronization
    5. 9.5 Programming
      1. 9.5.1 Interface and Control
      2. 9.5.2 I2C Serial Interface
        1. 9.5.2.1 I2C Block Register Transfers
      3. 9.5.3 SPI Serial Interface
        1. 9.5.3.1 SPI Block Register Transfer
      4. 9.5.4 Register Map Generation
      5. 9.5.5 General Register Programming Sequence
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Start-Up Sequence
      2. 10.1.2 Power Down (PD#) Pin
      3. 10.1.3 Strap Pins for Start-Up
      4. 10.1.4 ROM and EEPROM
      5. 10.1.5 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.1.5.1 Power-On Reset (POR) Circuit
        2. 10.1.5.2 Powering Up From a Single-Supply Rail
        3. 10.1.5.3 Power Up From Split-Supply Rails
        4. 10.1.5.4 Non-Monotonic or Slow Power-Up Supply Ramp
      6. 10.1.6 Slow or Delayed XO Start-Up
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Bypassing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Reliability
      1. 12.3.1 Support for PCB Temperature up to 105°C
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Glossary
    6. 13.6 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.2 Detailed Design Procedure

In a typical application, TI recommends the following steps:

  1. Use the device GUI in the TICS Pro programming software for a step-by-step design flow to enter the design parameters, calculate the frequency plan for each PLL domain, and generate the register settings for the desired configuration. The register settings can be exported (registers hex dump in txt format) to enable host programming.
    • A host device can program the register settings through the serial interface after power-up and issue a soft-reset (by SWRST bit) to start the device. Set SW_SYNC before, and clear after SWRST.
  2. Tie the GPIO1 pin to ground to select the I2C communications interface, or pull up GPIO1 high to VDD_DIG through an external resistor to select the SPI communications interface. Determine the logic I/O pin assignments for control and status functions. See Figure 9-36.
    • Connect I2C/SPI and logic I/O pins (1.8-V compatible levels) to the host device pins with the proper I/O direction and voltage levels.
  3. Select an XO frequency by following Section 9.3.1.
    • Choose an XO with target phase jitter performance that meets the frequency stability and accuracy requirements required for the output clocks during free-run or holdover.
    • For a 3.3-V LVCMOS driver, LMK5C33216 can accept it directly. Power the XO from a low-noise LDO regulator or optimize its power filtering to avoid supply noise-induced jitter on the XO clock.
    • TICS Pro: Configure the XO frequency to match the XO port input.
  4. Wire the clock I/O for each PLL domain in the schematic and use TICS Pro to configure the device settings as follows:
    • Reference inputs: Follow the LVCMOS or differential clock input interface examples in Figure 10-3 or Section 9.3.3.
      • TICS Pro: For DPLL mode, configure the reference input buffer modes to match the reference clock driver interface requirements. See Table 9-2.
    • TICS Pro: For DPLL mode, configure the DPLL input selection modes and input priorities. See Section 9.3.4.
    • TICS Pro: Configure each APLL reference from other VCO domain (Cascaded mode) or XO clock (Non-cascaded mode).
    • TICS Pro: Configure each output with the required clock frequency and PLL domain. TICS Pro can calculate the VCO frequencies and divider settings for the PLL and outputs. Consider the following output clock assignment guidelines to minimize crosstalk and spurs:
      • OUT[0:1] bank can select any PLL clocks, XO, and references.
      • OUT[2:3] bank is preferred for PLL1 or PLL2 clocks.
      • OUT[4:7] bank is preferred for PLL2 or PLL3 clocks.
      • OUT[8:13] bank is preferred for PLL3 or PLL2 clocks.
      • OUT[14:15] bank is preferred for PLL1, PLL2, or PLL3 clocks.
      • Group identical output frequencies (or harmonic frequencies) on adjacent channels, and use the output pairs with a single divider (for example, OUT2/3 or OUT14/15) when possible to minimize power.
      • Separate clock outputs when the difference of the two frequencies, |fOUTx – fOUTy|, falls within the jitter integration bandwidth (for example, 12 kHz to 20 MHz). Any outputs that are potential aggressors should be separated by at least four static pins (power pin, logic pin, or disabled output pins) to minimize potential coupling. If possible, separate these clocks by the placing them on opposite output banks, which are on opposite sides of the chip for best isolation.
      • Avoid or isolate any LVCMOS output (strong aggressor) from other jitter-sensitive differential output clocks. If an LVCMOS output is required, use dual complementary LVCMOS mode (+/- or -/+) with the unused LVCMOS output left floating with no trace.
      • If not all outputs pairs are used in the application, consider connecting an unused output to a pair of RF coaxial test structures for testing purposes (such as SMA, SMP ports).
    • TICS Pro: Configure the output drivers.
      • Configure the output driver modes to match the receiver clock input interface requirements. See Table 9-3.
      • Configure any output SYNC groups that need their output phases synchronized. See Section 9.3.17.
      • Configure the output auto-mute modes, and APLL and DPLL mute options. See Section 9.3.14.3.
    • Clock output Interfacing: Follow the single-ended or differential clock output interface examples in Figure 10-3 or Section 9.3.16.
      • Differential outputs can be AC-coupled and terminated and biased at the receiver inputs, or DC-coupled with proper receivers
      • LVCMOS outputs have internal source termination to drive 50-Ω traces directly. LVCMOS VOH level is determined by internal LDO programmed voltage (1.8 V or 2.65 V).
    • TICS Pro: Configure the DPLL loop bandwidth.
      • Below the loop bandwidth, the reference noise is added to the TDC noise floor and the XO/TCXO/OCXO noise. Above the loop bandwidth, the reference noise will be attenuated with roll-off up to 60 dB/decade. The optimal bandwidth depends on the relative phase noise between the reference input and the XO. APLL's loop bandwidth can be configured to provide additional attenuation of the reference input, TDC, and XO phase noise above APLL's bandwidth.
    • TICS Pro: Configure the maximum TDC frequency to optimize the DPLL TDC noise contribution for the desired use case.
      • Wired: A 400 kHz maximum TDC rate is commonly specified. This supports SyncE and other use cases using a narrow loop bandwidth (≤10 Hz) with a TCXO/OCXO/XO to set the frequency stability and wander performance.
      • Wireless: A 26 MHz maximum TDC rate is commonly specified for lowest in-band TDC noise contribution. This supports wireless and other use cases where close-in phase noise is critical.
    • TICS Pro: If clock steering is needed (such as for IEEE 1588 PTP), enable DCO mode for the DPLL loop and enter the frequency step size (in ppb). The FDEV step register will be computed according to Section 9.4.4.1.2. Enable the FDEV_TRIG and FDEV_DIR pin control on the GPIO pins if needed.
    • TICS Pro: If deterministic input-to-output clock phase is needed for 1-PPS input and 1-PPS output (on OUT0 or OUT1), enable the ZDM as required on OUT0, OUT4, or OUT10. See Section 9.3.18.
  5. TICS Pro: Configure the reference input monitoring options for each reference input. Disable the monitor when not required or when the input operates beyond the monitor's supported frequency range. See Section 9.3.7.2.
    • Frequency monitor: Set the valid and invalid thresholds (in ppm).
    • Missing pulse monitor: Set the late window threshold (TLATE) to allow for the longest expected input clock period, including worst-case cycle-to-cycle jitter. For a gapped clock input, set TLATE based on the number of allowable missing clock pulses.
    • Runt pulse monitor: Set the early window threshold (TEARLY) to allow for the shortest expected input clock period, including worst-case cycle-to-cycle jitter.
    • 1-PPS Phase validation monitor: Set the phase validation jitter threshold, including worst-case input cycle-to-cycle jitter.
    • Validation timer: Set the amount of time the reference input must be qualified by all enabled input monitors before the input is valid for selection.
  6. TICS Pro: Configure the DPLL lock detect and tuning word history monitoring options for each channel. See Section 9.3.7.3 and Section 9.3.7.4.
    • DPLL frequency lock and phase lock detectors: Set the lock and unlock thresholds for each detector.
  7. TICS Pro: Configure each status output pin and interrupt flag as needed. See Section 9.3.7.5 and Section 9.3.7.6.
    • Select the desired status signal selection, status polarity, and driver mode (3.3-V LVCMOS or open-drain). Open-drain requires an external pullup resistor.
    • If the Interrupt is enabled and selected as a status output, configure the flag polarity and the mask bits for any interrupt source, and the combinational OR gate, as needed.
  8. Consider the following guidelines for designing the power supply:
    • Outputs with identical frequency or integer-related (harmonic) frequencies can share a common filtered power supply.
      • Example: 156.25-MHz and 312.5-MHz outputs on OUT[4:5] and OUT[6:7] can share a filtered VDDO supply, while 100-MHz, 50-MHz, and 25-MHz outputs on OUT[0:1] and OUT[2:3] can share a separate VDDO supply.
    • See Section 10.1.5.