SNAS750B November 2020 – March 2021 LMK5C33216
PRODUCTION DATA
The Time of Day (ToD) counter allows the user to make a precise time measurement between two (or more) events. The events may be either a rising or falling edge of a GPIO pin or a falling edge of the SPI SCS pin. Any GPIO pin can be programmed for ToD Input. Rising or falling polarity can be chosen using the GPIO polarity invert register. After each ToD event, the counter values is captured and the application may read back a 40-bit value. The elapsed time is calculated based on the difference in the read back values. The accuracy of the measurement is better than 7.5 ns with a total measurement time over 59 minutes depending on exact configuration. It is necessary to read back at least the LSB of the TOD_CNTR to re-arm the ToD counter capture.
The ToD counter is clocked at a frequency based on PLL2 VCO frequency ÷ 20 or PLL3 VCO frequency ÷8. A time measurement is made by below steps.
The TOD_CNTR register is split across five registers.
PLL Source | VCO Frequency | ToD Clock Frequency | ToD Clock Period (t) | Roll-over time |
PLL3 | 2457.6 MHz | 307.2 MHz | ~3.225 ns | ~59.6 minutes |
PLL2 | 5950 MHz | 297.5 MHz | ~3.361 ns | ~61.6 minutes |
PLL2 | 5898.24 MHz | 294.912 MHz | ~3.391 ns | ~62.1 minutes |
PLL2 | 5625 MHz | 281.25 MHz | ~3.556 ns | ~65.1 minutes |
PLL2 | 5600 MHz | 280 MHz | ~3.571 ns | ~65.4 minutes |
Figure 9-32 illustrates the states of the Time of Day function.