SNAS750B November 2020 – March 2021 LMK5C33216
PRODUCTION DATA
The device can start up using I2C or SPI selected as the control interface depends on the 2-level input level sampled on the GPIO1 pin during power-on reset (POR). Internal register default settings after POR depend on the value of the ROM_PLUS_EE field stored in EEPROM.
After start-up, the I2C or SPI interface is enabled for register access to monitor the device status and control (or reconfigure) the device if needed. The register map configurations are the same for I2C and SPI.
The state of GPIO1 during POR determines:
The state of the EEPROM field EE_ROM_PAGE_SEL plus the GPIO0 and GPIO2 pins select the ROM page which will be used at start-up. If the field ROM_PLUS_EE is 0, then the device is started with just the ROM settings. If the field ROM_PLUS_EE is 1, then an EEPROM overlay is loaded and many fields controlling APLL and output clock configuration will be loaded from the EEPROM. This allows the user flexibility to select start-up clocks frequencies and output formats.
Figure 9-36 shows the device power-on reset configuration sequence.
Also see Figure 9-16, Figure 9-37, and Figure 9-38.