Isolate input, XO/OCXO/TCXO and output clocks from adjacent clocks with different frequencies and other nearby dynamic signals.
Consider the XO/OCXO/TCXO placement and layout in terms of the supply/ground noise and thermal gradients from nearby circuitry (for example, power supplies, FPGA, ASIC) as well as system-level vibration and shock. These factors can affect the frequency stability/accuracy and transient performance of the oscillator.
Avoid impedance discontinuities on controlled-impedance 50-Ω single-ended (or 100-Ω differential) traces for clock and dynamic logic signals.
Place bypass capacitors close to the VDD and VDDO pins on the same side as the IC, or directly below the IC pins on the opposite side of the PCB. Larger decoupling capacitor values can be placed further away.
Place external capacitors close to the CAP_x and LFx pins.
Use multiple vias to connect wide supply traces to the respective power islands or planes if possible.
Use at least a 6×6 through-hole via pattern to connect the IC ground/thermal pad to the PCB ground planes.
See the Land Pattern Example, Solder Mask Details, and Solder Paste Example in
Section 14.