SNAS848 December   2023 LMK5C33216A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
    2. 6.2 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 DPLL
        1. 7.2.2.1 Independent DPLL Operation
        2. 7.2.2.2 Cascaded DPLL Operation
        3. 7.2.2.3 APLL Cascaded with DPLL
      3. 7.2.3 APLL-Only Mode
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO)
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Clock Input Interfacing and Termination
      4. 7.3.4  Reference Input Mux Selection
        1. 7.3.4.1 Automatic Input Selection
        2. 7.3.4.2 Manual Input Selection
      5. 7.3.5  Hitless Switching
        1. 7.3.5.1 Hitless Switching With Phase Cancellation
        2. 7.3.5.2 Hitless Switching With Phase Slew Control
        3. 7.3.5.3 Hitless Switching With 1-PPS Inputs
      6. 7.3.6  Gapped Clock Support on Reference Inputs
      7. 7.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.7.1 XO Input Monitoring
        2. 7.3.7.2 Reference Input Monitoring
          1. 7.3.7.2.1 Reference Validation Timer
          2. 7.3.7.2.2 Frequency Monitoring
          3. 7.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 7.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 7.3.7.2.5 Phase Valid Monitor for 1-PPS Inputs
        3. 7.3.7.3 PLL Lock Detectors
        4. 7.3.7.4 Tuning Word History
        5. 7.3.7.5 Status Outputs
        6. 7.3.7.6 Interrupt
      8. 7.3.8  PLL Relationships
        1. 7.3.8.1  PLL Frequency Relationships
          1. 7.3.8.1.1 APLL Phase Detector Frequency
          2. 7.3.8.1.2 APLL VCO Frequency
          3. 7.3.8.1.3 DPLL TDC Frequency
          4. 7.3.8.1.4 DPLL VCO Frequency
          5. 7.3.8.1.5 Clock Output Frequency
        2. 7.3.8.2  Analog PLLs (APLL1, APLL2, APLL3)
        3. 7.3.8.3  APLL Reference Paths
          1. 7.3.8.3.1 APLL XO Doubler
          2. 7.3.8.3.2 APLL XO Reference (R) Divider
        4. 7.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 7.3.8.5  APLL Feedback Divider Paths
          1. 7.3.8.5.1 APLL N Divider With SDM
        6. 7.3.8.6  APLL Loop Filters (LF1, LF2, LF3)
        7. 7.3.8.7  APLL Voltage-Controlled Oscillators (VCO1, VCO2, VCO3)
          1. 7.3.8.7.1 VCO Calibration
        8. 7.3.8.8  APLL VCO Clock Distribution Paths
        9. 7.3.8.9  DPLL Reference (R) Divider Paths
        10. 7.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 7.3.8.11 DPLL Loop Filter (DLF)
        12. 7.3.8.12 DPLL Feedback (FB) Divider Path
      9. 7.3.9  Output Clock Distribution
      10. 7.3.10 Output Channel Muxes
      11. 7.3.11 Output Dividers (OD)
      12. 7.3.12 SYSREF/1-PPS
      13. 7.3.13 Output Delay
      14. 7.3.14 Clock Outputs (OUTx_P/N)
        1. 7.3.14.1 Differential Output
        2. 7.3.14.2 LVCMOS Output
        3. 7.3.14.3 SYSREF/1-PPS Output Replication
        4. 7.3.14.4 Output Auto-Mute During LOL
      15. 7.3.15 Glitchless Output Clock Start-Up
      16. 7.3.16 Clock Output Interfacing and Termination
      17. 7.3.17 Output Synchronization (SYNC)
      18. 7.3.18 Zero-Delay Mode (ZDM)
      19. 7.3.19 Time Elapsed Counter (TEC)
        1. 7.3.19.1 Configuring TEC Functionality
        2. 7.3.19.2 SPI as a Trigger Source
        3. 7.3.19.3 GPIO Pin as a TEC Trigger Source
          1. 7.3.19.3.1 An Example: Making a Time Elapsed Measurement Using TEC and GPIO1 as Trigger
        4. 7.3.19.4 TEC Timing
        5. 7.3.19.5 Other TEC Behavior
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Start-Up
        1. 7.4.1.1 ROM Selection
        2. 7.4.1.2 EEPROM Overlay
      2. 7.4.2 DPLL Operating States
        1. 7.4.2.1 Free-Run
        2. 7.4.2.2 Lock Acquisition
        3. 7.4.2.3 DPLL Locked
        4. 7.4.2.4 Holdover
      3. 7.4.3 PLL Start-Up Sequence
      4. 7.4.4 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 7.4.4.1 DPLL DCO Control
          1. 7.4.4.1.1 DPLL DCO Relative Adjustment Frequency Step Size
          2. 7.4.4.1.2 APLL DCO Frequency Step Size
      5. 7.4.5 APLL Frequency Control
      6. 7.4.6 DPLL Programmable Phase Delay
    5. 7.5 Programming
      1. 7.5.1 Interface and Control
      2. 7.5.2 I2C Serial Interface
        1. 7.5.2.1 I2C Block Register Transfers
      3. 7.5.3 SPI Serial Interface
        1. 7.5.3.1 SPI Block Register Transfer
      4. 7.5.4 Register Map Generation
      5. 7.5.5 General Register Programming Sequence
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PD#) Pin
      3. 8.1.3 Strap Pins for Start-Up
      4. 8.1.4 Pin States
      5. 8.1.5 ROM and EEPROM
      6. 8.1.6 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.6.1 Power-On Reset (POR) Circuit
        2. 8.1.6.2 Powering Up From a Single-Supply Rail
        3. 8.1.6.3 Power Up From Split-Supply Rails
        4. 8.1.6.4 Non-Monotonic or Slow Power-Up Supply Ramp
      7. 8.1.7 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Clock Tree Architect Programming Software
        2. 9.1.1.2 Texas Instruments Clocks and Synthesizers (TICS) Pro Software
        3. 9.1.1.3 PLLatinum™ Simulation Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Glossary
    7. 9.7 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Typical Characteristics

GUID-34BCB903-70AD-45D6-BD2A-91E3948608CB-low.png
Jitter = 44 fs RMS (12 kHz to 20 MHz)
fAPLL3 = 2457.6 MHz
Figure 5-8 491.52-MHz HSDS output from APLL3 BAW
GUID-20231201-SS0I-TSF3-NQ6V-L3FJHSBMMBBZ-low.png
Jitter = 57 fs RMS (12 kHz to 20 MHz)
fAPLL3 = 2457.6 MHz
Figure 5-10 122.88-MHz HSDS output from APLL3 BAW
GUID-A5CA0C90-FD5B-4F0A-B433-6BD017C1B220-low.png
A.
Figure 5-12 312.5-MHz HSDS output from APLL2
GUID-20220718-SS0I-PJGT-VQNX-ZXNVNVKR8BQX-low.svg
Jitter = 101 fs RMS (12 kHz to 20 MHz)
fAPLL2 = 5800.78125 MHz
Figure 5-14 161.1328125-MHz HSDS output from APLL2
GUID-20220718-SS0I-PBSC-VRQF-8QB5MHWTJD6R-low.svg
Jitter = 100 fs RMS (12 kHz to 20 MHz)
fAPLL2 = 5836.8 MHz
Figure 5-16 153.6-MHz HSDS output from APLL2
GUID-20220718-SS0I-MXXN-MPGS-THM88Q76TPTZ-low.svg
Jitter = 230 fs RMS (12 kHz to 20 MHz)
fAPLL1 = 5200 MHz
Figure 5-18 100-MHz HSDS output from APLL1
GUID-20231201-SS0I-QJGN-2RG6-88H23BQW6C3N-low.png
Jitter = 51 fs RMS (12 kHz to 20 MHz)
fAPLL3 = 2457.6 MHz
Figure 5-9 245.76-MHz HSDS output from APLL3 BAW
GUID-20220718-SS0I-5Z2X-2MXQ-MSZWXCXBQ6QL-low.svg
Jitter = 98 fs RMS (12 kHz to 20 MHz)
fAPLL2 = 5800.78125 MHz
Figure 5-11 322.265625-MHz HSDS output from APLL2
GUID-20220718-SS0I-T5LH-MZSC-XMTTLSWKV3TD-low.svg
Jitter = 103 fs RMS (12 kHz to 20 MHz)
fAPLL2 = 5950 MHz
Figure 5-13 212.5-MHz HSDS output from APLL2
GUID-20220718-SS0I-SVXN-TD2T-DQSZHM74CBLN-low.svg
Jitter = 101 fs RMS (12 kHz to 20 MHz)
fAPLL2 = 5598.72 MHz
Figure 5-15 155.52-MHz HSDS output from APLL2
GUID-3E341601-F71C-492A-A645-CC7799DCEB03-low.png
A.
Figure 5-17 312.5-MHz HSDS output from APLL1
GUID-20220718-SS0I-TJTV-Z0H0-KP9PDZ0V04LT-low.svg
Jitter = 345 fs RMS (12 kHz to 20 MHz)
fAPLL1 = 5200 MHz
Figure 5-19 50-MHz HSDS output from APLL1

GUID-20220718-SS0I-FXSX-2PKJ-P9LVG2XSSVCW-low.svg
Figure 5-20 SYSREF/1-PPS Delay Linearity vs Analog Delay Code 2

GUID-20220718-SS0I-BLJ2-LTZP-J2QB46WFML6N-low.svg
Figure 5-22 SYSREF/1-PPS Delay Linearity vs Analog Delay Code 4

GUID-20220718-SS0I-K02C-TRNF-1X3ZKHBJ4DHN-low.svg
Figure 5-21 SYSREF/1-PPS Delay Linearity vs Analog Delay Code 3

GUID-20220718-SS0I-KXCK-GJMD-X9TS7LCX1KP3-low.svg
Figure 5-23 SYSREF/1-PPS Delay Linearity vs Analog Delay Code 5