The LMK5C33414AS1 has four reference inputs, three digital PLLs (DPLLs), three analog PLLs (APLLs) with integrated VCOs, and 14 output clocks. APLL3 uses an ultra-high performance BAW VCO (VCBO) with a very high quality factor, and thus minimizes dependency on the phase noise or frequency of the external oscillator (XO) input clock. TI's VCBO technology reduces the overall solution cost to meet the free-run and holdover frequency stability requirements. TI recommends an XO, TCXO, or OCXO based on system holdover stability requirements. Each APLL can be controlled by the corresponding DPLL, allowing the APLL domain to be locked to the DPLL reference input for synchronous clock generation. Each APLL can select a reference from XO port or another APLL divided clock. Each DPLL can select a synchronization input reference from reference inputs INx or align to another APLL domain by selecting feedback from one of the cascade dividers.

The DPLL reference input mux supports automatic input selection based on priority and reference signal monitoring criteria. Manual input selection is also possible through software or pin control. The device provides hitless switching between reference sources with proprietary phase cancellation and phase slew control for superior phase buildout and transient performance. The reference clock input monitoring block monitors the clock inputs and will perform a hitless switchover or holdover when a loss of reference (LOR) is detected. A LOR condition will be detected upon any violation of the threshold limits set for the input monitors, which include frequency, missing and early pulse, runt pulse, and 1-PPS (pulse-per-second) detectors. The threshold limits for each input detector can be set and enabled per reference clock input. The tuning word history monitor feature determines the initial output frequency accuracy upon entry into holdover based on the historical average frequency when locked, thereby minimizing the frequency and phase disturbance during a LOR condition.

The LMK5C33414AS1 has 14 outputs with programmable output driver types, allowing up to 14 differential clocks, or a combination of differential and single-ended clocks. Up to four single-ended 1.8-V or 2.65-V LVCMOS clocks (each from _P and _N outputs from OUT0 and OUT1). Each output clock derives from one of three APLL/VCO domains through the output muxes. Output 0 (OUT0) and Output 1 (OUT1) are the most flexible and may select their source from the XO, reference input, or any APLL domain. A SYSREF or 1-PPS output can be supported on Output 0 (OUT0) and Output 1 (OUT1) as well as any other differential output sourced from a SYSREF/1-PPS divider. The output dividers have a SYNC feature to allow multiple outputs to be phase-aligned. ZDM can also achieve a deterministic phase alignment between a clock from any DPLL presented to OUT0 and the selected reference input. ZDM feedback paths are also available on OUT10 for DPLL3 and OUT4 for DPLL2.

To support IEEE 1588 PTP secondary clock or other clock steering applications, the DPLL supports DCO mode with less than 1-ppt (part per trillion) frequency resolution for precise frequency and phase adjustment through software or pin control.

The device is fully programmable through I²C or SPI and supports start-up frequency configuration with factory pre-programmed internal ROM pages. A programmable EEPROM overlay, which allows POR configuration of registers related to APLL and output configuration, provides flexible power up output clocks. Internal LDO regulators provide excellent PSNR to reduce the cost and complexity of the power delivery network. The clock input and PLL monitoring status are visible through the GPIO status pins and interrupt registers readback for full diagnostic capability.