SNAS718C December   2016  – December 2017 LMK60E0-156M , LMK60E0-212M , LMK60E2-100M , LMK60E2-125M , LMK60E2-156M , LMK60I2-100M , LMK60I2-322M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 Frequency Tolerance Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 PSRR Characteristics
    13. 6.13 PLL Clock Output Jitter Characteristics
    14. 6.14 Additional Reliability and Qualification
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Ensuring Thermal Reliability
      2. 9.1.2 Best Practices for Signal Integrity
      3. 9.1.3 Recommended Solder Reflow Profile
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • SIA|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

SIA Package
6-pin QFM
Top View
LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M pinout_snas676.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
POWER
GND 3 Ground Device ground
VDD 6 Analog 3.3-V power supply
OUTPUT BLOCK
OUTP, OUTN 4, 5 Universal Differential output pair (LVPECL, LVDS or HCSL).
DIGITAL CONTROL / INTERFACES
NC 2 N/A No connect
OE 1 LVCMOS Output enable (internal pullup). When set to low, output pair is disabled and set at high impedance.