SNAS805 June 2020 LMK61E08
PRODUCTION DATA.
The PLL_FRACDEN_BY0 register is described in the following table.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:0] | PLL_DEN[7:0] | RW | 0xFF | Y | PLL Fractional Divider Denominator Byte 0. Bits [7:0]. |