LMK61E0M Ultra-Low Jitter Programmable Oscillator With Internal EEPROM

1 Features

• Ultra-Low Noise, High Performance
  • Jitter: 500-fs RMS Typical f_OUT > 50 MHz on LMK61E0M
• LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
• Total Frequency Tolerance of ±25 ppm
• System Level Features
  • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
  • Internal EEPROM: User Configurable Start-Up Settings
• Other Features
  • Device Control: Fast Mode I²C up to 1000 kHz
  • 3.3-V Operating Voltage
  • Industrial Temperature Range (–40ºC to +85ºC)
  • 7-mm × 5-mm 8-Pin Package
• Default Frequency: 70.656 MHz

2 Applications

• High-Performance Replacement for Crystal, SAW, or Silicon-Based Oscillators
• Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
• Test and Measurement
• Medical Imaging
• FPGA, Processor Attach
• xDSL, Broadcast Video

3 Description

The LMK61E0 family of ultra-low jitter PLLatinum^TM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I²C serial interface. The device provides fine and coarse frequency margining control through I²C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Pinout and Simplified Block Diagram

4 Revision History

Changes from * Revision (January 2017) to A Revision

• Updated data sheet text to the latest documentation and translations standardsGo
• Corrected recommended junction temperature Go
• Corrected junction temperature Go
• Updated register namesGo
• Typical application schematic added Go

5 Pin Configuration and Functions

SIA Package

8-Pin QFM

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