SNAS674B September   2015  – February 2017 LMK61E2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 ADD Input Characteristics
    11. 6.11 Frequency Tolerance Characteristics
    12. 6.12 Power-On/Reset Characteristics (VDD)
    13. 6.13 I2C-Compatible Interface Characteristics (SDA, SCL)
    14. 6.14 PSRR Characteristics
    15. 6.15 Other Characteristics
    16. 6.16 PLL Clock Output Jitter Characteristics
    17. 6.17 Typical 156.25-MHz Output Phase Noise Characteristics
    18. 6.18 Typical 161.1328125 MHz Output Phase Noise Characteristics
    19. 6.19 Additional Reliability and Qualification
    20. 6.20 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Block-Level Description
      2. 8.3.2  Device Configuration Control
      3. 8.3.3  Register File Reference Convention
      4. 8.3.4  Configuring the PLL
      5. 8.3.5  Integrated Oscillator
      6. 8.3.6  Reference Doubler
      7. 8.3.7  Phase Frequency Detector
      8. 8.3.8  Feedback Divider (N)
      9. 8.3.9  Fractional Circuitry
      10. 8.3.10 Charge Pump
      11. 8.3.11 Loop Filter
      12. 8.3.12 VCO Calibration
      13. 8.3.13 High-Speed Output Divider
      14. 8.3.14 High-Speed Clock Output
      15. 8.3.15 Device Status
        1. 8.3.15.1 Loss of Lock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interface and Control
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
    6. 8.6 EEPROM Map
    7. 8.7 Register Map
      1. 8.7.1 Register Descriptions
        1. 8.7.1.1  VNDRID_BY1 Register; R0
        2. 8.7.1.2  VNDRID_BY0 Register; R1
        3. 8.7.1.3  PRODID Register; R2
        4. 8.7.1.4  REVID Register; R3
        5. 8.7.1.5  SLAVEADR Register; R8
        6. 8.7.1.6  EEREV Register; R9
        7. 8.7.1.7  DEV_CTL Register; R10
        8. 8.7.1.8  XO_CAPCTRL_BY1 Register; R16
        9. 8.7.1.9  XO_CAPCTRL_BY0 Register; R17
        10. 8.7.1.10 DIFFCTL Register; R21
        11. 8.7.1.11 OUTDIV_BY1 Register; R22
        12. 8.7.1.12 OUTDIV_BY0 Register; R23
        13. 8.7.1.13 PLL_NDIV_BY1 Register; R25
        14. 8.7.1.14 PLL_NDIV_BY0 Register; R26
        15. 8.7.1.15 PLL_FRACNUM_BY2 Register; R27
        16. 8.7.1.16 PLL_FRACNUM_BY1 Register; R28
        17. 8.7.1.17 PLL_FRACNUM_BY0 Register; R29
        18. 8.7.1.18 PLL_FRACDEN_BY2 Register; R30
        19. 8.7.1.19 PLL_FRACDEN_BY1 Register; R31
        20. 8.7.1.20 PLL_FRACDEN_BY0 Register; R32
        21. 8.7.1.21 PLL_MASHCTRL Register; R33
        22. 8.7.1.22 PLL_CTRL0 Register; R34
        23. 8.7.1.23 PLL_CTRL1 Register; R35
        24. 8.7.1.24 PLL_LF_R2 Register; R36
        25. 8.7.1.25 PLL_LF_C1 Register; R37
        26. 8.7.1.26 PLL_LF_R3 Register; R38
        27. 8.7.1.27 PLL_LF_C3 Register; R39
        28. 8.7.1.28 PLL_CALCTRL Register; R42
        29. 8.7.1.29 NVMSCRC Register; R47
        30. 8.7.1.30 NVMCNT Register; R48
        31. 8.7.1.31 NVMCTL Register; R49
        32. 8.7.1.32 MEMADR Register; R51
        33. 8.7.1.33 NVMDAT Register; R52
        34. 8.7.1.34 RAMDAT Register; R53
        35. 8.7.1.35 NVMUNLK Register; R56
        36. 8.7.1.36 INT_LIVE Register; R66
        37. 8.7.1.37 SWRST Register; R72
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Jitter Considerations in Serdes Systems
      2. 9.2.2 Frequency Margining
        1. 9.2.2.1 Fine Frequency Margining
        2. 9.2.2.2 Coarse Frequency Margining
      3. 9.2.3 Design Requirements
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 Custom Design With WEBENCH® Tools
          2. 9.2.3.1.2 Device Selection
          3. 9.2.3.1.3 VCO Frequency Calculation
          4. 9.2.3.1.4 Device Configuration
          5. 9.2.3.1.5 PLL Loop Filter Design
          6. 9.2.3.1.6 Spur Mitigation Techniques
            1. 9.2.3.1.6.1 Phase Detection Spur
            2. 9.2.3.1.6.2 Integer Boundary Fractional Spur
            3. 9.2.3.1.6.3 Primary Fractional Spur
            4. 9.2.3.1.6.4 Sub-Fractional Spur
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ensured Thermal Reliability
      2. 11.1.2 Best Practices for Signal Integrity
      3. 11.1.3 Recommended Solder Reflow Profile
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

For development support, see the following:

12.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMK61E2 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.5 Trademarks

PLLatinum, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.