SNAS675A October   2015  – November 2015 LMK61PD0A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Control
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - Power Supply
    6. 7.6  LVPECL Output Characteristics
    7. 7.7  LVDS Output Characteristics
    8. 7.8  HCSL Output Characteristics
    9. 7.9  OE Input Characteristics
    10. 7.10 OS, FS[1:0] Input Characteristics
    11. 7.11 Frequency Tolerance Characteristics
    12. 7.12 Power-On/Reset Characteristics (VDD)
    13. 7.13 PSRR Characteristics
    14. 7.14 PLL Clock Output Jitter Characteristics
    15. 7.15 Additional Reliability and Qualification
    16. 7.16 Typical Performance Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Device Output Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Block-Level Description
      2. 9.3.2 Device Configuration Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Jitter Considerations in Serdes Systems
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ensuring Thermal Reliability
      2. 12.1.2 Best Practices for Signal Integrity
      3. 12.1.3 Recommended Solder Reflow Profile
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Power Supply Recommendations

For best electrical performance of LMK61PD0A2, it is preferred to utilize a combination of 10 uF, 1 uF and 0.1 uF on its power supply bypass network. It is also recommended to utilize component side mounting of the power supply bypass capacitors and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low impedance connection to the ground plane. Figure 16 shows the layout recommendation for power supply decoupling of LMK61PD0A2.