SNAS826E April   2022  – April 2024 LMK6C , LMK6D , LMK6H , LMK6P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Ordering Information
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bulk Acoustic Wave (BAW)
      2. 8.3.2 Device Block-Level Description
      3. 8.3.3 Function Pins
      4. 8.3.4 Clock Output Interfacing and Termination
      5. 8.3.5 Temperature Stability
      6. 8.3.6 Mechanical Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics

 over Recommended Operating Conditions, Typical Temp = 25°C, Frequency output = 156.25 MHz, VDD = 3.3 V, LVCMOS Output Capacitor load = 2.2 pF (unless otherwise specified)(7)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption Characteristics
IDD Device Power Consumption (LVPECL,VDD = 2.5 V/3.3 V, Excluding load current) 100 MHz 65 82 mA
156.25 MHz 69 87 mA
200 MHz 67 85 mA
312.5 MHz 76 95 mA
400 MHz 88 108 mA
Device Power Consumption (LVPECL,VDD = 1.8 V, Excluding load current) 100 MHz 61 79 mA
156.25 MHz 66 83 mA
200 MHz 64 82 mA
312.5 MHz 73 91 mA
400 MHz 84 104 mA
Device Power Consumption (HCSL,VDD = 2.5 V/3.3 V, Excluding load current) 100 MHz 65 82 mA
156.25 MHz 69 87 mA
200 MHz 67 86 mA
312.5 MHz 76 96 mA
400 MHz 88 108 mA
Device Power Consumption  (HCSL,VDD = 1.8 V, Excluding load current) 100 MHz 58 75 mA
156.25 MHz 62 80 mA
200 MHz 60 78 mA
312.5 MHz 69 88 mA
400 MHz 77 97 mA
Device Power Consumption  (LVDS,VDD = 2.5 V/3.3 V, Excluding load current) 100 MHz 54 71 mA
156.25 MHz 58 75 mA
200 MHz 56 74 mA
312.5 MHz 65 84 mA
400 MHz 76 96 mA
Device Power Consumption  (LVDS,VDD = 1.8 V, Excluding load current) 100 MHz 52 68 mA
156.25 MHz 56 72 mA
200 MHz 54 71 mA
312.5 MHz 63 80 mA
400 MHz 74 92 mA
Device Power Consumption  (LVCMOS,VDD = 2.5 V / 3.3 V, with load) 100 MHz 45 62 mA
156.25 MHz 55 71 mA
200 MHz 61 77 mA
Device Power Consumption  (LVCMOS,VDD = 1.8 V, with load) 100 MHz 44 59 mA
156.25 MHz 50 65 mA
200 MHz 56 72 mA
IDD-STBY Device Stand By current ST (Stand By) = GND 6 13 mA
IDD-PD Device current with output disabled (100 MHz) OE = GND, LVPECL mode, VDD = 3.3 V 48 67 mA
OE = GND, HCSL mode, VDD = 3.3 V 49 67 mA
OE = GND, LVDS mode, VDD = 3.3 V 49 66 mA
OE = GND, LVCMOS mode, VDD = 3.3 V 40 56 mA
LVPECL Output Characteristics
Fout Output Frequency 1 400 MHz
VOD Output Voltage Swing (VOH - VOL) AC coupled, VDD = 3.3V 525 645 765 mV
AC coupled, VDD = 2.5V 450 555 660 mV
AC coupled, VDD = 1.8 V 280 375 470 mV
DC coupled, VDD = 2.5 V/ 3.3 V(1) 650 800 950 mV
DC coupled, VDD = 1.8 V(1) 450 600 750 mV
VOD,DIFF Differential Output peak-peak swing 2×|VOD| Vpp
VOS Output Common-Mode Voltage VDD = 3.3 V(1) 1.5 1.6 1.7 V
VDD = 2.5 V(1) 0.825 0.9 0.975 V
VDD = 1.8 V(1) 0.45 0.5 0.55 V
tR/tF Output Rise/Fall Time 20% to 80% of VOD,DIFF, VDD = 2.5 V/ 3.3 V 120 200 ps
20% to 80% of VOD,DIFF, VDD = 1.8 V 120 200 ps
ODC Output Duty Cycle VDD = 2.5 V/ 3.3V, measured between 50% points on the waveform 45 50 55 %
VDD = 1.8 V, measured between 50% points on the waveform 45 50 55 %
LVDS Output Characteristics
Fout Output Frequency 1 400 MHz
VOD Output Voltage Swing (VOH - VOL) Under LVDS Load condition 250 350 450 mV
VOD,DIFF Differential Output peak-peak swing 2×|VOD| Vpp
VOS Output Common Mode Voltage VDD = 2.5V/3.3 V 1.025 1.2 1.375 V
VDD = 1.8 V 0.80 0.9 1.0 V
tR/tF Output Rise/Fall Time 20% to 80% of VOD,DIFF, VDD = 2.5V/3.3 V 150 250 ps
20% to 80% of VOD,DIFF, VDD = 1.8V 150 250 ps
ODC Output Duty Cycle VDD = 2.5 V/3.3 V, measured between 50% points on the waveform 45 50 55 %
VDD = 1.8V, measured between 50% points on the waveform 45 50 55 %
HCSL Output characteristics
Fout Output Frequency 1 400 MHz
VOH Output High Voltage DC coupled, 50 ohms to ground, VDD = 2.5 V/ 3.3 V 650 750 850 mV
DC coupled, 50 ohms to ground, VDD = 1.8 V 460 560 660 mV
VOL Output Low Voltage DC coupled, 50 ohms to ground, VDD = 2.5 V/ 3.3 V  –150 0 150 mV
DC coupled, 50 ohms to ground, VDD = 1.8 V –150 0 150 mV
VOD,DIFF Differential Output peak-peak swing 2×|VOH - VOL| V
Vcross Absolute Crossing Point Voltage VDD = 3.3 V / 2.5 V, fout = 100 MHz 0.2 0.35 0.50 Vpp
VDD = 1.8 V, fout = 100 MHz 0.15 0.275 0.40 Vpp
Vcross-delta Absolute Crossing Point Voltage variation VDD = 3.3 V / 2.5 V / 1.8 V, fout = 100 MHz 0.14 V
dV/dt Output Slew Rate 50 ohms to ground; DC coupled load; measured slew rate in +/-150mV from Center.  2 12 V/ns
ΔdV/dt Output  Slew Rate variation 20 %
ODC Output Duty Cycle 45 50 55 %
LVCMOS Output Characteristics
Fout Output Frequency 1 200 MHz
VOL Output Low Voltage IOL = 3.6 mA, VDD = 1.8 V 0.36 V
IOL = 5.0 mA, VDD = 2.5 V 0.5 V
IOL = 6.6 mA, VDD = 3.3 V 0.66 V
VOH Output High Voltage IOH = 3.6 mA, VDD = 1.8 V 1.44 V
IOH = 5.0 mA, VDD = 2.5 V 2 V
IOH = 6.6 mA, VDD = 3.3 V 2.64 V
tR/tF Output Rise/Fall Time 20% to 80% of VOH -VOL, CL = 2 pF 0.5 1 ns
ODC Output Duty Cycle 45 50 55 %
Rout Output Impedance OE = HIGH 40 50 60 Ω
CL Maximum capacitive load Fout > 50 MHz(3) 15 pF
Fout < 50 MHz(3) 30 pF
Function Pin Input Characteristics (OE/ST pin)
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 1.3 V
IIL Input Low Current OE = GND -40 µA
IIH Input High Current OE = VDD 40 µA
CIN Input Capacitance 2 pF
LVDS, HCSL and LVPECL Frequency Tolerance
FT Total Frequency Stability Inclusive of: solder shift, initial tolerance, variation over -40℃ to 85℃, variation over rated supply voltage range, and 10 year aging at 25℃. –25 25 ppm
Inclusive of: solder shift, initial tolerance, variation over -40℃ to 85℃, variation over supply voltage range. –20 20 ppm
LVCMOS Frequency Tolerance
FT Total Frequency Stability Inclusive of: solder shift, initial tolerance, variation over -40℃ to 105℃, variation over rated supply voltage range, and 10 year aging at 25℃. -25 25 ppm
Inclusive of: solder shift, initial tolerance, variation over -40℃ to 105℃, variation over rated supply voltage range. -20 20 ppm
Differential output PSRR Characteristics
PSRR Spur induced by 50 mV power supply ripple at 156.25 MHz output, VDD = 2.5 V/3.3 V, No power supply decoupling capacitor Sine wave at 50 kHz –71 dBc
Sine wave at 100 kHz –71 dBc
Sine wave at 500 kHz –72 dBc
Sine wave at 1 MHz –70 dBc
PSRR Spur induced by 50 mV power supply ripple at 156.25 MHz output, VDD = 1.8 V, No power supply decoupling capacitor Sine wave at 50 kHz –64 dBc
Sine wave at 100 kHz –64 dBc
Sine wave at 500 kHz –67 dBc
Sine wave at 1 MHz –68 dBc
PSRR Jitter sensitivity to Power supply ripple;  100 kHz sine wave ripple, 3.3 V Supply(2) 4 fs/mV
LVCMOS PSRR Characteristics
PSRR Spur induced by 50 mV power supply ripple at 50MHz output, VDD = 2.5V/3.3 V, No power supply decoupling capacitor Sine wave at 50 kHz –72 dBc
Sine wave at 100 kHz –71 dBc
Sine wave at 500 kHz –70 dBc
Sine wave at 1 MHz –69 dBc
PSRR Spur induced by 50 mV power supply ripple at 50MHz output, VDD = 1.8V, No power supply decoupling capacitor Sine wave at 50 kHz –50 dBc
Sine wave at 100 kHz –50 dBc
Sine wave at 500 kHz –52 dBc
Sine wave at 1 MHz –55 dBc
PSRR Jitter sensitivity to Power supply ripple;  100 kHz sine wave ripple, 3.3 V Supply(2) 10 fs/mV
Power-On Characteristics
tSTART_UP Start-up Time Time elapsed from 0.95 x VDD until output is enabled and output is within specification; Tested with a VDD supply ramp time of around 200 μs  5 ms
tOE-EN Output Enable Time Time elapsed from OE = VIH until output is enabled and output is within specification, Fout > 10 MHz 25 µs
tOE-DIS Output Disable Time Time elapsed from OE = VIL until output is disabled, Fout > 10 MHz 1 µs
LVPECL - Clock Output Jitter

RJ
 		 RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 156.25 MHz 100 125 fs
PN1k Phase Noise at 1 kHz Offset Fout = 156.25 MHz. –95 dBc/Hz
PN10k Phase Noise at 10 kHz Offset –127 dBc/Hz
PN100k Phase Noise at 100 kHz Offset –146 dBc/Hz
PN1M Phase Noise at 1 MHz Offset –156 dBc/Hz
PN10M Phase Noise at 10 MHz Offset –158 dBc/Hz

RJ
 		 RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 312.5 MHz 100 125 fs
PN1k Phase Noise at 1 kHz Offset Fout = 312.5 MHz. –89 dBc/Hz
PN10k Phase Noise at 10 kHz Offset –121 dBc/Hz
PN100k Phase Noise at 100 kHz Offset –140 dBc/Hz
PN1M Phase Noise at 1 MHz Offset –150 dBc/Hz
PN10M Phase Noise at 10 MHz Offset –154 dBc/Hz
RJ RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 100 MHz 125 170 fs
Fout = 125 MHz 100 125 fs
Fout = 155.52 MHz 100 125 fs
Fout = 161.1328125 MHz 110 150 fs
Fout = 200 MHz 120 150 fs
Fout = 400 MHz 100 135 fs
RPeriodJITT,RMS RMS Period Jitter Fout ≥ 25 MHz 1.7 ps
RJITT,PK-PK Peak-peak Period Jitter Fout ≥ 25 MHz 13 ps
LVDS - Clock Output Jitter

RJ
 		 RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 156.25 MHz 100 125 fs
PN1k Phase Noise at 1 kHz Offset Fout = 156.25 MHz –95 dBc/Hz
PN10k Phase Noise at 10 kHz Offset –128 dBc/Hz
PN100k Phase Noise at 100 kHz Offset –146 dBc/Hz
PN1M Phase Noise at 1 MHz Offset –156 dBc/Hz
PN10M Phase Noise at 10 MHz Offset –156.5 dBc/Hz

RJ
 		 RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 312.5 MHz 100 125 fs
PN1k Phase Noise at 1 kHz Offset Fout = 312.5 MHz. –89 dBc/Hz
PN10k Phase Noise at 10 kHz Offset –122 dBc/Hz
PN100k Phase Noise at 100 kHz Offset –139 dBc/Hz
PN1M Phase Noise at 1 MHz Offset –150 dBc/Hz
PN10M Phase Noise at 10 MHz Offset –153.5 dBc/Hz
RJ RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 100 MHz 140 170 fs
Fout = 125 MHz 110 125 fs
Fout = 155.52 MHz 105 140 fs
Fout = 161.1328125 MHz 125 160 fs
Fout = 200 MHz 125 150 fs
Fout = 400 MHz 100 135 fs
RPeriodJITT,RMS RMS Period Jitter Fout ≥ 25 MHz 1.6 ps
RJITT,PK-PK Peak-peak Period Jitter Fout ≥ 25 MHz 13 ps
HCSL - Clock output jitter
JPCIe1-cc PCIe Gen 1 Common Clock jitter (jitter limit = 86 ps) Fout = 100 MHz 0.146 6.4 ps
JPCIe1-SRNS PCIe Gen 1 SRNS jitter 0.447 6.99 ps
JPCIe2-cc PCIe Gen 2 Common Clock jitter (jitter limit = 3 ps) 0.103 0.554 ps
JPCIe2-SRNS PCIe Gen 2 SRNS jitter 0.135 0.56 ps
JPCIe3-cc PCIe Gen 3 Common Clock jitter (jitter limit = 1 ps) 0.029 0.164 ps
JPCIe3-SRNS PCIe Gen 3 SRNS jitter 0.033 0.180 ps
JPCIe4-cc PCIe Gen 4 Common Clock jitter (jitter limit = 500 fs) 0.029 0.164 ps
JPCIe4-SRNS PCIe Gen 4 SRNS jitter 0.033 0.180 ps
JPCIe5-cc PCIe Gen 5 Common Clock jitter (jitter limit = 150 fs) 0.007 0.070 ps
JPCIe5-SRNS PCIe Gen 5 SRNS jitter 0.007 0.074 ps
JPCIe6-cc PCIe Gen 6 Common Clock jitter (jitter limit = 100 fs) 0.007 0.042 ps
JPCIe6-SRNS PCIe Gen 6 SRNS jitter 0.009 0.052 ps

RJ

 		 RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 156.25 MHz 100 125 fs
PN1k Phase Noise at 1 kHz Offset Fout = 156.25 MHz. –95 dBc/Hz
PN10k Phase Noise at 10 kHz Offset –127 dBc/Hz
PN100k Phase Noise at 100 kHz Offset –146 dBc/Hz
PN1M Phase Noise at 1 MHz Offset –156 dBc/Hz
PN10M Phase Noise at 10 MHz Offset –158 dBc/Hz

RJ

 		 RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 312.5 MHz 100 125 fs
PN1k Phase Noise at 1 kHz Offset Fout = 312.5 MHz. –89 dBc/Hz
PN10k Phase Noise at 10 kHz Offset –121 dBc/Hz
PN100k Phase Noise at 100 kHz Offset –140 dBc/Hz
PN1M Phase Noise at 1 MHz Offset –150 dBc/Hz
PN10M Phase Noise at 10 MHz Offset –154 dBc/Hz
RJ RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 100 MHz 125 170 fs
Fout = 125 MHz 100 125 fs
Fout = 155.52 MHz 100 125 fs
Fout = 161.1328125 MHz 110 150 fs
Fout = 200 MHz 120 150 fs
Fout = 400 MHz 100 135 fs
RPeriodJITT,RMS RMS Period Jitter Fout ≥ 25 MHz 1.7 ps
RJITT,PK-PK Peak-peak Period Jitter Fout ≥ 25 MHz 13 ps
LVCMOS - Clock Output Jitter
RJ RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 156.25 MHz 0.25 0.5 ps
PN1k Phase Noise at 1 kHz Offset Fout = 156.25 MHz –100 dBc/Hz
PN10k Phase Noise at 10 kHz Offset –128 dBc/Hz
PN100k Phase Noise at 100 kHz Offset –143 dBc/Hz
PN1M Phase Noise at 1 MHz Offset –150 dBc/Hz
PN10M Phase Noise at 10 MHz Offset –152 dBc/Hz
RJ RMS Jitter (Integration BW: 12 kHz to 5 MHz) Fout = 24 MHz 0.25 0.5 ps
Fout = 25 MHz 0.25 0.5 ps
Fout = 33.33 MHz 0.25 1 ps
RMS Jitter (Integration BW: 12 kHz to 20 MHz) Fout = 40 MHz 0.5 1 ps
Fout = 50 MHz 0.4 1 ps
Fout = 66.66 MHz 0.5 1 ps
Fout = 74.25 MHz 0.3 0.5 ps
Fout = 78 MHz 0.35 0.5 ps
Fout = 100 MHz 0.35 0.5 ps
Fout = 125 MHz 0.35 0.5 ps
RPeriodJITT,RMS RMS Period Jitter Fout ≥ 25 MHz 1.5 ps
RJITT,PK-PK Peak-peak Period Jitter Fout ≥ 25 MHz 13 ps
(1) DC Load condition
(2) Measured using TI LMK6x Evaluation Module;
(3) Refer to Application Curves section for Rise time and fall time details for different capacitor load values.
(4) The Jitter specifications are based on design and characterization