SNAS855D November 2023 – June 2024 LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204
PRODUCTION DATA
Table 9-29 lists the memory-mapped registers for the LMKDB1108 registers. All register offset addresses not listed in Table 9-29 must be considered as reserved locations and the register contents must not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | R0 | Output Enable Control for CLK2 through CLK7 | Section 9.2.1 |
1h | R1 | Output Enable Control for CLK0 and CLK1 | Section 9.2.2 |
2h | R2 | OE Pin Readback for CLK2 through CLK7 | Section 9.2.3 |
3h | R3 | OE Pin Readback for CLK0 and CLK1 | Section 9.2.4 |
4h | R4 | AOD Enable Control and SBI_EN Readback | Section 9.2.5 |
5h | R5 | Device Info | Section 9.2.6 |
6h | R6 | Device Info (cont.) | Section 9.2.7 |
7h | R7 | SMBus Byte Counter | Section 9.2.8 |
8h | R8 | SBI Mask for CLK2 through CLK7 | Section 9.2.9 |
9h | R9 | SBI Mask for CLK0 and CLK1 | Section 9.2.10 |
Bh | R11 | SBI Mask Readback for CLK0 through CLK5 | Section 9.2.11 |
Ch | R12 | SBI Mask Readback for CLK6 and CLK7 | Section 9.2.12 |
11h | R17 | Output Amplitude | Section 9.2.13 |
12h | R18 | Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS Readback | Section 9.2.14 |
14h | R20 | Output Slew Rate Select MSB for CLK2 through CLK7 | Section 9.2.15 |
15h | R21 | Output Slew Rate Select MSB for CLK0 and CLK1 | Section 9.2.16 |
26h | R38 | Non-clearable SMBUS Write Lock | Section 9.2.17 |
27h | R39 | LOS Event Status and Clearable SMBus Write Lock | Section 9.2.18 |
35h | R53 | Slew Rate Mode Control Selection | Section 9.2.19 |
5Bh | R91 | Slew Rate Speed Options 1 and 2 Assignments | Section 9.2.20 |
5Ch | R92 | Slew Rate Speed Options 3 and 4 Assignments | Section 9.2.21 |
62h | R98 | Output Slew Rate Select LSB for CLK0 through CLK7 | Section 9.2.22 |
Complex bit access types are encoded to fit into small table cells. Table 9-30 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RC | R C |
Read to Clear |
Write Type | ||
W | W | Write |
W1C | W 1C |
Write 1 to clear |
WSC | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
R0 is shown in Table 9-31.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLK_EN_2 | R/W | 1h | Output Enable for CLK2 0h = Output Disabled (low/low) 1h = Output Enabled |
6 | CLK_EN_3 | R/W | 1h | Output Enable for CLK3 0h = Output Disabled (low/low) 1h = Output Enabled |
5 | CLK_EN_4 | R/W | 1h | Output Enable for CLK4 0h = Output Disabled (low/low) 1h = Output Enabled |
4 | RESERVED | R | 0h | Reserved |
3 | CLK_EN_5 | R/W | 1h | Output Enable for CLK5 0h = Output Disabled (low/low) 1h = Output Enabled |
2 | CLK_EN_6 | R/W | 1h | Output Enable for CLK6 0h = Output Disabled (low/low) 1h = Output Enabled |
1 | CLK_EN_7 | R/W | 1h | Output Enable for CLK7 0h = Output Disabled (low/low) 1h = Output Enabled |
0 | RESERVED | R | 0h | Reserved |
R1 is shown in Table 9-32.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | CLK_EN_0 | R/W | 1h | Output Enable for CLK0 0h = Output Disabled (low/low) 1h = Output Enabled |
4:3 | RESERVED | R | 0h | Reserved |
2 | CLK_EN_1 | R/W | 1h | Output Enable for CLK1 0h = Output Disabled (low/low) 1h = Output Enabled |
1:0 | RESERVED | R | 0h | Reserved |
R2 is shown in Table 9-33.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RB_OEb_2 | R | 0h | Status of OEb2 |
6 | RB_OEb_3 | R | 0h | Status of OEb3 |
5 | RB_OEb_4 | R | 0h | Status of OEb4 |
4 | RESERVED | R | 0h | Reserved |
3 | RB_OEb_5 | R | 0h | Status of OEb5 |
2 | RB_OEb_6 | R | 0h | Status of OEb6 |
1 | RB_OEb_7 | R | 0h | Status of OEb7 |
0 | RESERVED | R | 0h | Reserved |
R3 is shown in Table 9-34.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | RB_OEb_0 | R | 0h | Status of OEb0 |
4:3 | RESERVED | R | 0h | Reserved |
2 | RB_OEb_1 | R | 0h | Status of OEb1 |
1:0 | RESERVED | R | 0h | Reserved |
R4 is shown in Table 9-35.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0h | Reserved |
4 | AOD_ENABLE | R/W | 1h | Enable automatic output disable (AOD)
to low/low when LOS event is detected. Refer to
section "Automatic Output Disable" for more
information. 0h = Disabled (DC Coupled) 1h = Enabled (AC Coupled) |
3:1 | RESERVED | R | 0h | Reserved |
0 | RB_SBI_ENQ | R | 0h | Status of SBI_ENQ |
R5 is shown in Table 9-36.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | REV_ID | R | 0h | Revision ID |
3:0 | VENDOR_ID | R | Ah | Vendor ID |
R6 is shown in Table 9-37.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | DEV_ID | R | 8h | Device ID |
R7 is shown in Table 9-38.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0h | Reserved |
4:0 | SMBUS_BC | R/W | 7h | SMBUS Block Read Byte Count |
R8 is shown in Table 9-39.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SBI_MASK_2 | R/W | 0h | Mask off Side-Band Disable for CLK2 |
6 | SBI_MASK_3 | R/W | 0h | Mask off Side-Band Disable for CLK3 |
5 | SBI_MASK_4 | R/W | 0h | Mask off Side-Band Disable for CLK4 |
4 | RESERVED | R | 0h | Reserved |
3 | SBI_MASK_5 | R/W | 0h | Mask off Side-Band Disable for CLK5 |
2 | SBI_MASK_6 | R/W | 0h | Mask off Side-Band Disable for CLK6 |
1 | SBI_MASK_7 | R/W | 0h | Mask off Side-Band Disable for CLK7 |
0 | RESERVED | R | 0h | Reserved |
R9 is shown in Table 9-40.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | SBI_MASK_0 | R/W | 0h | Mask off Side-Band Disable for CLK0 |
4:3 | RESERVED | R | 0h | Reserved |
2 | SBI_MASK_1 | R/W | 0h | Mask off Side-Band Disable for CLK1 |
1:0 | RESERVED | R | 0h | Reserved |
R11 is shown in Table 9-41.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SBI_CLK_2 | R | 1h | Readback of Side-Band Disable for CLK5 |
6 | SBI_CLK_3 | R | 1h | Readback of Side-Band Disable for CLK4 |
5 | SBI_CLK_4 | R | 1h | Readback of Side-Band Disable for CLK3 |
4 | RESERVED | R | 0h | Reserved |
3 | SBI_CLK_5 | R | 1h | Readback of Side-Band Disable for CLK2 |
2 | SBI_CLK_6 | R | 1h | Readback of Side-Band Disable for CLK1 |
1 | SBI_CLK_7 | R | 1h | Readback of Side-Band Disable for CLK0 |
0 | RESERVED | R | 0h | Reserved |
R12 is shown in Table 9-42.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | SBI_CLK_0 | R | 1h | Readback of Side-Band Disable for CLK7 |
4:3 | RESERVED | R | 0h | Reserved |
2 | SBI_CLK_1 | R | 1h | Readback of Side-Band Disable for CLK6 |
1:0 | RESERVED | R | 0h | Reserved |
R17 is shown in Table 9-43.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | AMP | R/W | 6h | Global Differential output Control
0.6V to 1V 25mV/step Default = 0.8V 0h = 600mV 1h = 625mV 2h = 650mV 3h = 675mV 4h = 700mV 5h = 725mV 6h = 750mV 7h = 775mV 8h = 800mV 9h = 825mV Ah = 850mV Bh = 875mV Ch = 900mV Dh = 925mV Eh = 950mV Fh = 975mV |
3:0 | RESERVED | R | 0h | Reserved |
R18 is shown in Table 9-44.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RX_EN_AC_INPUT | R/W | 0h | Enable receiver bias when CLKIN is AC
coupled 0h = DC Coupled Input 1h = AC Coupled Input |
6 | RX_EN_RTERM_LSB | R/W | 0h | Enable/Disables termination resistors
on CLKIN1 0h = Disabled 1h = Enabled |
5:4 | RESERVED | R | 0h | Reserved |
3 | PD_RESTOREB | R/W | 1h | Save Configuration in Power Down 0h = Config Cleared 1h = Config Saved |
2:1 | RESERVED | R | 0h | Reserved |
0 | LOSb_RB | R | 0h | Real time read back of loss detect
block output 0h = LOS Event Detected 1h = LOS Event Not-Detected |
R20 is shown in Table 9-45.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SLEWRATE_SEL_CLK2_MSB | R/W | 1h | MSB CLK2 slew rate select |
6 | SLEWRATE_SEL_CLK3_MSB | R/W | 1h | MSB CLK3 slew rate select |
5 | SLEWRATE_SEL_CLK4_MSB | R/W | 1h | MSB CLK4 slew rate select |
4 | RESERVED | R | 0h | Reserved |
3 | SLEWRATE_SEL_CLK5_MSB | R/W | 1h | MSB CLK5 slew rate select |
2 | SLEWRATE_SEL_CLK6_MSB | R/W | 1h | MSB CLK6 slew rate select |
1 | SLEWRATE_SEL_CLK7_MSB | R/W | 1h | MSB CLK7 slew rate select |
0 | RESERVED | R | 0h | Reserved |
R21 is shown in Table 9-46.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | SLEWRATE_SEL_CLK0_MSB | R/W | 1h | MSB CLK0 slew rate select |
4:3 | RESERVED | R | 0h | Reserved |
2 | SLEWRATE_SEL_CLK1_MSB | R/W | 1h | MSB CLK1 slew rate select |
1:0 | RESERVED | R | 0h | Reserved |
R38 is shown in Table 9-47.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R | 0h | Reserved |
0 | WRITE_LOCK | R | 0h | Non-clearable SMBus Write Lock bit.
When written to one, the SMBus control registers
cannot be written to. This bit can only be cleared
by recycling power. 0h = SMBus Not Locked for Writing 1h = SMBus Locked for Writing |
R39 is shown in Table 9-48.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R | 0h | Reserved |
1 | LOS_EVT | R/W | 0h | LOS Event Status. When high, indicates
that a LOS event is detected. Can be cleared by
writing a 1. 0h = Not LOS Event Detected 1h = LOS Event Detected |
0 | WRITE_LOCK_RW1C | R | 0h | Clearable SMBus Write Lock bit. When
written to one, the SMBus control registers can not
be written to. This bit can be cleared by writing a
1. 0h = SMBus Not Locked for Writing 1h = SMBus Locked for Writing |
R53 is shown in Table 9-49.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | SLEWRATE_CTRL_MODE | R/WSC | 0h | Sets which mode is used to change the
outputs slew rates 0h = Pin mode 1h = SMBus mode |
4:0 | RESERVED | R | 0h | Reserved |
R91 is shown in Table 9-50.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | SLEWRATE_OPT_2 | R/W | 6h | There are four register assignments
each storing a slew rate value (chosen out of the 16
available slew rate values). This register bits
relate to the 2nd option. Go to Programmable Output
Slew Rate section for more information. 0h = 0 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 |
3:0 | SLEWRATE_OPT_1 | R/W | 0h | There are four register assignments
each storing a slew rate value (chosen out of the 16
available slew rate values). This register bits
relate to the 1st option. Go to Programmable Output
Slew Rate section for more information. 0h = 0 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 |
R92 is shown in Table 9-51.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | SLEWRATE_OPT_4 | R/W | Fh | There are four register assignments
each storing a slew rate value (chosen out of the 16
available slew rate values). This register bits
relate to the 4th option. Go to Programmable Output
Slew Rate section for more information. 0h = 0 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 |
3:0 | SLEWRATE_OPT_3 | R/W | Ah | There are four register assignments
each storing a slew rate value (chosen out of the 16
available slew rate values). This register bits
relate to the 3rd option. Go to Programmable Output
Slew Rate section for more information. 0h = 0 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 |
R98 is shown in Table 9-52.
Return to the Table 9-29.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SLEWRATE_SEL_CLK7_LSB | R/W | 0h | LSB CLK7 Slew Rate Control |
6 | SLEWRATE_SEL_CLK6_LSB | R/W | 0h | LSB CLK6 Slew Rate Control |
5 | SLEWRATE_SEL_CLK5_LSB | R/W | 0h | LSB CLK5 Slew Rate Control |
4 | SLEWRATE_SEL_CLK4_LSB | R/W | 0h | LSB CLK4 Slew Rate Control |
3 | SLEWRATE_SEL_CLK3_LSB | R/W | 0h | LSB CLK3 Slew Rate Control |
2 | SLEWRATE_SEL_CLK2_LSB | R/W | 0h | LSB CLK2 Slew Rate Control |
1 | SLEWRATE_SEL_CLK1_LSB | R/W | 0h | LSB CLK1 Slew Rate Control |
0 | SLEWRATE_SEL_CLK0_LSB | R/W | 0h | LSB CLK0 Slew Rate Control |