SNAS855D November 2023 – June 2024 LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204
PRODUCTION DATA
Table 9-77 lists the memory-mapped registers for the LMKDB1204 registers. All register offset addresses not listed in Table 9-77 must be considered as reserved locations and the register contents must not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | R0 | Output Enable Control for CLK2 and CLK3 | Section 9.4.1 |
1h | R1 | Output Enable Control for CLK0 and CLK1 | Section 9.4.2 |
2h | R2 | OE Pin Readback for CLK2 and CLK3 | Section 9.4.3 |
3h | R3 | OE Pin Readback for CLK0 and CLK1 | Section 9.4.4 |
4h | R4 | CLKIN1 AOD Enable Control | Section 9.4.5 |
5h | R5 | Device Info | Section 9.4.6 |
6h | R6 | Device Info (cont.) | Section 9.4.7 |
7h | R7 | SMBus Byte Counter | Section 9.4.8 |
11h | R17 | Output Amplitude | Section 9.4.9 |
12h | R18 | Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS Readback | Section 9.4.10 |
14h | R20 | Output Slew Rate Select MSB for CLK2 and CLK3 | Section 9.4.11 |
15h | R21 | Output Slew Rate Select MSB for CLK0 and CLK1 | Section 9.4.12 |
24h | R36 | CLKIN0 AOD Enable Control | Section 9.4.13 |
26h | R38 | Non-clearable SMBUS Write Lock | Section 9.4.14 |
27h | R39 | LOS Event Status and Clearable SMBus Write Lock | Section 9.4.15 |
2Bh | R43 | CLKIN Source Select | Section 9.4.16 |
5Bh | R91 | Slew Rate Speed Options 1 and 2 Assignments | Section 9.4.17 |
5Ch | R92 | Slew Rate Speed Options 3 and 4 Assignments | Section 9.4.18 |
5Dh | R93 | CLKIN0 AC/DC coupled Selection | Section 9.4.19 |
62h | R98 | Output Slew Rate Select LSB for CLK0 and CLK1 | Section 9.4.20 |
63h | R99 | Output Slew Rate Select LSB for CLK2 and CLK3 | Section 9.4.21 |
Complex bit access types are encoded to fit into small table cells. Table 9-78 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
Reset or Default Value | ||
-n | Value after reset or the default value |
R0 is shown in Table 9-79.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | CLK_EN_1 | R/W | 1h | Output Enable for CLK1
0h = Output Disabled (low/low) 1h = Output Enabled |
4 | RESERVED | R | 0h | Reserved |
3 | CLK_EN_0 | R/W | 1h | Output Enable for CLK0
0h = Output Disabled (low/low) 1h = Output Enabled |
2:0 | RESERVED | R | 0h | Reserved |
R1 is shown in Table 9-80.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0h | Reserved |
4 | CLK_EN_3 | R/W | 1h | Output Enable for CLK3
0h = Output Disabled (low/low) 1h = Output Enabled |
3 | RESERVED | R | 0h | Reserved |
2 | CLK_EN_2 | R/W | 1h | Output Enable for CLK2
0h = Output Disabled (low/low) 1h = Output Enabled |
1:0 | RESERVED | R | 0h | Reserved |
R2 is shown in Table 9-81.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | RB_OEb_1 | R | 0h | Status of OEb1 |
4 | RESERVED | R | 0h | Reserved |
3 | RB_OEb_0 | R | 0h | Status of OEb0 |
2:0 | RESERVED | R | 0h | Reserved |
R3 is shown in Table 9-82.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0h | Reserved |
4 | RB_OEb_3 | R | 0h | Status of OEb3 |
3 | RESERVED | R | 0h | Reserved |
2 | RB_OEb_2 | R | 0h | Status of OEb2 |
1:0 | RESERVED | R | 0h | Reserved |
R4 is shown in Table 9-83.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0h | Reserved |
4 | CLKIN1_AOD_ENABLE | R/W | 1h | Enable automatic output disable (AOD) for CLKIN1 to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Inactive 1h = Active |
3:0 | RESERVED | R | 0h | Reserved |
R5 is shown in Table 9-84.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | REV_ID | R | 0h | Revision ID |
3:0 | VENDOR_ID | R | Ah | Vendor ID |
R6 is shown in Table 9-85.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | DEV_ID | R | 24h | Device ID |
R7 is shown in Table 9-86.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0h | Reserved |
4:0 | SMBUS_BC | R/W | 7h | SMBUS Block Read Byte Count |
R17 is shown in Table 9-87.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | AMP_BANK1 | R/W | 6h | Global Differential output Control,approximately 0.6V to 1V 25mV/step (default = 0.75V)
0h = 600 mV 1h = 625 mV 2h = 650 mV 3h = 675 mV 4h = 700 mV 5h = 725 mV 6h = 750 mV 7h = 775 mV 8h = 800 mV 9h = 825 mV Ah = 850 mV Bh = 875 mV Ch = 900 mV Dh = 925 mV Eh = 950 mV Fh = 975 mV |
3:0 | AMP_BANK0 | R/W | 6h | Global Differential output Control,approximately 0.6V to 1V 25mV/step (default = 0.75V)
0h = 600 mV 1h = 625 mV 2h = 650 mV 3h = 675 mV 4h = 700 mV 5h = 725 mV 6h = 750 mV 7h = 775 mV 8h = 800 mV 9h = 825 mV Ah = 850 mV Bh = 875 mV Ch = 900 mV Dh = 925 mV Eh = 950 mV Fh = 975 mV |
R18 is shown in Table 9-88.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RX_CLKIN1_EN_AC_INPUT | R/W | 0h | Enable receiver bias when CLKIN1 is AC coupled
0h = DC Coupled Input 1h = AC Coupled Input |
6 | RX_CLKIN1_EN_RTERM | R/W | 0h | Enable termination resistors on CLKIN1
0h = Input termination inactive 1h = Input termination active |
5 | RX_CLKIN0_EN_RTERM | R/W | 0h | Enable termination resistors on CLKIN0
0h = Input termination inactive 1h = Input termination active |
4 | RESERVED | R | 0h | Reserved |
3 | PD_RESTOREB | R | 1h | Save configuration in powerdown
0h = Config Cleared 1h = Config Saved |
2 | RESERVED | R | 0h | Reserved |
1 | SDATA_TIMEOUT_EN | R | 1h | Enable SMBus SDATA time out monitoring
0h = Disable SDATA timeout 1h = Enable SDATA timeout |
0 | LOSb_RB | R | 0h | Real time read back of loss detect block output
0h = LOS Event Detected 1h = LOS Event Not-Detected |
R20 is shown in Table 9-89.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | SLEWRATE_SEL_CLK1_MSB | R/W | 1h | MSB CLK1 slew rate select |
4 | RESERVED | R | 0h | Reserved |
3 | SLEWRATE_SEL_CLK0_MSB | R/W | 1h | MSB CLK0 slew rate select |
2:0 | RESERVED | R | 0h | Reserved |
R21 is shown in Table 9-90.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0h | Reserved |
4 | SLEWRATE_SEL_CLK3_MSB | R/W | 1h | MSB CLK3 slew rate select |
3 | RESERVED | R | 0h | Reserved |
2 | SLEWRATE_SEL_CLK2_MSB | R/W | 1h | MSB CLK2 slew rate select |
1:0 | RESERVED | R | 0h | Reserved |
R36 is shown in Table 9-91.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R | 0h | Reserved |
3 | CLKIN0_AOD_ENABLE | R/W | 1h | Enable automatic output disable (AOD) for CLKIN0 to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Inactive 1h = Active |
2:0 | RESERVED | R | 0h | Reserved |
R38 is shown in Table 9-92.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R | 0h | Reserved |
0 | WRITE_LOCK | R | 0h | Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power.
0h = SMBus Not Locked for Writing 1h = SMBus Locked for Writing |
R39 is shown in Table 9-93.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | RESERVED | R | 0h | Reserved |
1 | LOS_EVT | R | 0h | LOS Event Status. When high, indicates that a LOS event is detected. Can be
cleared by writing a 1. 0h = Not LOS Event Detected 1h = LOS Event Detected |
0 | WRITE_LOCK_RW1C | R/W1C | 0h | Clearable SMBus Write Lock bit. When written to one, the SMBus control registers
can not be written to. This bit can be cleared by
writing a 1. 0h = SMBus Not Locked for Writing 1h = SMBus Locked for Writing |
R43 is shown in Table 9-94.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5:4 | CLKIN_SEL | R/W | 0h | CLKIN Source Select
0h = All outputs come from CLKIN0 1h = CLKIN0 inputs go to BANK0 and CLKIN1 inputs go to BANK1 2h = Invalid 3h = All outputs come from CLKIN1 |
3:0 | RESERVED | R | 0h | Reserved |
R91 is shown in Table 9-95.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | SLEWRATE_OPT_2 | R/W | 6h | There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 2nd option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest) 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 (slowest) |
3:0 | SLEWRATE_OPT_1 | R/W | 0h | There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 1st option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest) 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 (slowest) |
R92 is shown in Table 9-96.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | SLEWRATE_OPT_4 | R/W | Fh | There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 4th option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest) 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 (slowest) |
3:0 | SLEWRATE_OPT_3 | R/W | Ah | There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 3rd option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest) 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 8h = 8 9h = 9 Ah = 10 Bh = 11 Ch = 12 Dh = 13 Eh = 14 Fh = 15 (slowest) |
R93 is shown in Table 9-97.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:1 | RESERVED | R | 0h | Reserved |
0 | RX_CLKIN0_EN_AC_INPUT | R/W | 0h | Enable receiver bias when CLKIN0 is AC coupled
0h = DC Coupled Input 1h = AC Coupled Input |
R98 is shown in Table 9-98.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0h | Reserved |
5 | SLEWRATE_SEL_CLK2_LSB | R/W | 0h | LSB CLK2 Slew Rate Control |
4 | SLEWRATE_SEL_CLK3_LSB | R/W | 0h | LSB CLK3 Slew Rate Control |
3:0 | RESERVED | R | 0h | Reserved |
R99 is shown in Table 9-99.
Return to the Table 9-77.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6 | SLEWRATE_SEL_CLK0_LSB | R/W | 0h | LSB CLK0 Slew Rate Control |
5:3 | RESERVED | R | 0h | Reserved |
2 | SLEWRATE_SEL_CLK1_LSB | R/W | 0h | LSB CLK1 Slew Rate Control |
1:0 | RESERVED | R | 0h | Reserved |