SNAS855D November   2023  – June 2024 LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Output Banks
        2. 8.3.4.2 Double Termination
        3. 8.3.4.3 Programmable Output Slew Rate
          1. 8.3.4.3.1 Slew Rate Control through Pin
          2. 8.3.4.3.2 Slew Rate Control through SMBus
        4. 8.3.4.4 Programmable Output Swing
        5. 8.3.4.5 Accurate Output Impedance
        6. 8.3.4.6 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1104 Registers
    4. 9.4 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Overview

LMKDB11xx are DB2000QL compliant clock buffers that distribute either 20 (LMKDB1120), or 8 (LMKDB1108) LP-HCSL clocks (respectively) designed for PCIe Gen 1 through 6 applications. LMKDB12xx are DB2000QL compliant clock muxes that can distribute 4 (LMKDB1204) and 2 (LMKDB1202) LP-HCSL clock outputs from two clock input sources.

With ultra-low additive jitter and ultra-low propagation delay, both devices allow for enough jitter margin for the entire clock path mainly required for PCIe Gen 5 and Gen 6 buffer cascading and Ethernet fan-out applications. The LMKDB11xx and LMKDB12xx also support both 1.8 V and 3.3 V supply voltages for better design flexibility.

LMKDB11xx and LMKDB12xx have individual OE controls for all outputs, which provides more design flexibility. Each output of each device also has programmable slew rate, programmable output amplitude swing, and automatic output disable. The devices support 100-Ω or 85-Ω LP-HCSL, denoted by the part number as shown in Section 4, with output frequencies of up to 400 MHz. LMKDB12xx devices have ZOUT_SEL pin to select 100-Ω or 85-Ω LP-HCSL output impedance.

LMKDB11xx have pin mode, SMBus mode, and Side Band Interface (SBI) mode, which can all be used at the same time. While LMKDB12xx only offers pin mode and SMBus mode. The vSMB_EN pin on LMKDB12xx can be used to select pin mode or SMBus mode. SBI enables or disables output clocks at a much faster speeds (up to 25 MHz) as compared to SMBus. Furthermore, because both SBI and SMBus can operate at the same time, SMBus can still be used to take over device control and readback status after power-up. For more details please refer to Section 8.4

Refer to Section 8 for the detailed descriptions of the devices pins and the Register Map for more details on the device registers.