SNAS855D November   2023  – June 2024 LMKDB1108 , LMKDB1120 , LMKDB1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Output Banks
        2. 8.3.4.2 Double Termination
        3. 8.3.4.3 Programmable Output Slew Rate
          1. 8.3.4.3.1 Slew Rate Control through Pin
          2. 8.3.4.3.2 Slew Rate Control through SMBus
        4. 8.3.4.4 Programmable Output Swing
        5. 8.3.4.5 Accurate Output Impedance
        6. 8.3.4.6 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1104 Registers
    4. 9.4 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2 LMKDB1108 Registers

Table 9-29 lists the memory-mapped registers for the LMKDB1108 registers. All register offset addresses not listed in Table 9-29 must be considered as reserved locations and the register contents must not be modified.

Table 9-29 LMKDB1108 Registers
Offset Acronym Register Name Section
0h R0 Output Enable Control for CLK2 through CLK7 Section 9.2.1
1h R1 Output Enable Control for CLK0 and CLK1 Section 9.2.2
2h R2 OE Pin Readback for CLK2 through CLK7 Section 9.2.3
3h R3 OE Pin Readback for CLK0 and CLK1 Section 9.2.4
4h R4 AOD Enable Control and SBI_EN Readback Section 9.2.5
5h R5 Device Info Section 9.2.6
6h R6 Device Info (cont.) Section 9.2.7
7h R7 SMBus Byte Counter Section 9.2.8
8h R8 SBI Mask for CLK2 through CLK7 Section 9.2.9
9h R9 SBI Mask for CLK0 and CLK1 Section 9.2.10
Bh R11 SBI Mask Readback for CLK0 through CLK5 Section 9.2.11
Ch R12 SBI Mask Readback for CLK6 and CLK7 Section 9.2.12
11h R17 Output Amplitude Section 9.2.13
12h R18 Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS Readback Section 9.2.14
14h R20 Output Slew Rate Select MSB for CLK2 through CLK7 Section 9.2.15
15h R21 Output Slew Rate Select MSB for CLK0 and CLK1 Section 9.2.16
26h R38 Non-clearable SMBUS Write Lock Section 9.2.17
27h R39 LOS Event Status and Clearable SMBus Write Lock Section 9.2.18
35h R53 Slew Rate Mode Control Selection Section 9.2.19
5Bh R91 Slew Rate Speed Options 1 and 2 Assignments Section 9.2.20
5Ch R92 Slew Rate Speed Options 3 and 4 Assignments Section 9.2.21
62h R98 Output Slew Rate Select LSB for CLK0 through CLK7 Section 9.2.22

Complex bit access types are encoded to fit into small table cells. Table 9-30 shows the codes that are used for access types in this section.

Table 9-30 LMKDB1108 Access Type Codes
Access Type Code Description
Read Type
R R Read
RC R
C		 Read
to Clear
Write Type
W W Write
W1C W
1C		 Write
1 to clear
WSC W Write
Reset or Default Value
-n Value after reset or the default value

9.2.1 R0 Register (Offset = 0h) [Reset = EEh]

R0 is shown in Table 9-31.

Return to the Table 9-29.

Table 9-31 R0 Register Field Descriptions
Bit Field Type Reset Description
7 CLK_EN_2 R/W 1h Output Enable for CLK2
0h = Output Disabled (low/low)
1h = Output Enabled
6 CLK_EN_3 R/W 1h Output Enable for CLK3
0h = Output Disabled (low/low)
1h = Output Enabled
5 CLK_EN_4 R/W 1h Output Enable for CLK4
0h = Output Disabled (low/low)
1h = Output Enabled
4 RESERVED R 0h Reserved
3 CLK_EN_5 R/W 1h Output Enable for CLK5
0h = Output Disabled (low/low)
1h = Output Enabled
2 CLK_EN_6 R/W 1h Output Enable for CLK6
0h = Output Disabled (low/low)
1h = Output Enabled
1 CLK_EN_7 R/W 1h Output Enable for CLK7
0h = Output Disabled (low/low)
1h = Output Enabled
0 RESERVED R 0h Reserved

9.2.2 R1 Register (Offset = 1h) [Reset = 24h]

R1 is shown in Table 9-32.

Return to the Table 9-29.

Table 9-32 R1 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 CLK_EN_0 R/W 1h Output Enable for CLK0
0h = Output Disabled (low/low)
1h = Output Enabled
4:3 RESERVED R 0h Reserved
2 CLK_EN_1 R/W 1h Output Enable for CLK1
0h = Output Disabled (low/low)
1h = Output Enabled
1:0 RESERVED R 0h Reserved

9.2.3 R2 Register (Offset = 2h) [Reset = 00h]

R2 is shown in Table 9-33.

Return to the Table 9-29.

Table 9-33 R2 Register Field Descriptions
Bit Field Type Reset Description
7 RB_OEb_2 R 0h Status of OEb2
6 RB_OEb_3 R 0h Status of OEb3
5 RB_OEb_4 R 0h Status of OEb4
4 RESERVED R 0h Reserved
3 RB_OEb_5 R 0h Status of OEb5
2 RB_OEb_6 R 0h Status of OEb6
1 RB_OEb_7 R 0h Status of OEb7
0 RESERVED R 0h Reserved

9.2.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 9-34.

Return to the Table 9-29.

Table 9-34 R3 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 RB_OEb_0 R 0h Status of OEb0
4:3 RESERVED R 0h Reserved
2 RB_OEb_1 R 0h Status of OEb1
1:0 RESERVED R 0h Reserved

9.2.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 9-35.

Return to the Table 9-29.

Table 9-35 R4 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4 AOD_ENABLE R/W 1h Enable automatic output disable (AOD) to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Disabled (DC Coupled)
1h = Enabled (AC Coupled)
3:1 RESERVED R 0h Reserved
0 RB_SBI_ENQ R 0h Status of SBI_ENQ

9.2.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 9-36.

Return to the Table 9-29.

Table 9-36 R5 Register Field Descriptions
Bit Field Type Reset Description
7:4 REV_ID R 0h Revision ID
3:0 VENDOR_ID R Ah Vendor ID

9.2.7 R6 Register (Offset = 6h) [Reset = 08h]

R6 is shown in Table 9-37.

Return to the Table 9-29.

Table 9-37 R6 Register Field Descriptions
Bit Field Type Reset Description
7:0 DEV_ID R 8h Device ID

9.2.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 9-38.

Return to the Table 9-29.

Table 9-38 R7 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4:0 SMBUS_BC R/W 7h SMBUS Block Read Byte Count

9.2.9 R8 Register (Offset = 8h) [Reset = 00h]

R8 is shown in Table 9-39.

Return to the Table 9-29.

Table 9-39 R8 Register Field Descriptions
Bit Field Type Reset Description
7 SBI_MASK_2 R/W 0h Mask off Side-Band Disable for CLK2
6 SBI_MASK_3 R/W 0h Mask off Side-Band Disable for CLK3
5 SBI_MASK_4 R/W 0h Mask off Side-Band Disable for CLK4
4 RESERVED R 0h Reserved
3 SBI_MASK_5 R/W 0h Mask off Side-Band Disable for CLK5
2 SBI_MASK_6 R/W 0h Mask off Side-Band Disable for CLK6
1 SBI_MASK_7 R/W 0h Mask off Side-Band Disable for CLK7
0 RESERVED R 0h Reserved

9.2.10 R9 Register (Offset = 9h) [Reset = 00h]

R9 is shown in Table 9-40.

Return to the Table 9-29.

Table 9-40 R9 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SBI_MASK_0 R/W 0h Mask off Side-Band Disable for CLK0
4:3 RESERVED R 0h Reserved
2 SBI_MASK_1 R/W 0h Mask off Side-Band Disable for CLK1
1:0 RESERVED R 0h Reserved

9.2.11 R11 Register (Offset = Bh) [Reset = EEh]

R11 is shown in Table 9-41.

Return to the Table 9-29.

Table 9-41 R11 Register Field Descriptions
Bit Field Type Reset Description
7 SBI_CLK_2 R 1h Readback of Side-Band Disable for CLK5
6 SBI_CLK_3 R 1h Readback of Side-Band Disable for CLK4
5 SBI_CLK_4 R 1h Readback of Side-Band Disable for CLK3
4 RESERVED R 0h Reserved
3 SBI_CLK_5 R 1h Readback of Side-Band Disable for CLK2
2 SBI_CLK_6 R 1h Readback of Side-Band Disable for CLK1
1 SBI_CLK_7 R 1h Readback of Side-Band Disable for CLK0
0 RESERVED R 0h Reserved

9.2.12 R12 Register (Offset = Ch) [Reset = 24h]

R12 is shown in Table 9-42.

Return to the Table 9-29.

Table 9-42 R12 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SBI_CLK_0 R 1h Readback of Side-Band Disable for CLK7
4:3 RESERVED R 0h Reserved
2 SBI_CLK_1 R 1h Readback of Side-Band Disable for CLK6
1:0 RESERVED R 0h Reserved

9.2.13 R17 Register (Offset = 11h) [Reset = 66h]

R17 is shown in Table 9-43.

Return to the Table 9-29.

Table 9-43 R17 Register Field Descriptions
Bit Field Type Reset Description
7:4 AMP R/W 6h Global Differential output Control 0.6V to 1V 25mV/step Default = 0.8V
0h = 600mV
1h = 625mV
2h = 650mV
3h = 675mV
4h = 700mV
5h = 725mV
6h = 750mV
7h = 775mV
8h = 800mV
9h = 825mV
Ah = 850mV
Bh = 875mV
Ch = 900mV
Dh = 925mV
Eh = 950mV
Fh = 975mV
3:0 RESERVED R 0h Reserved

9.2.14 R18 Register (Offset = 12h) [Reset = 08h]

R18 is shown in Table 9-44.

Return to the Table 9-29.

Table 9-44 R18 Register Field Descriptions
Bit Field Type Reset Description
7 RX_EN_AC_INPUT R/W 0h Enable receiver bias when CLKIN is AC coupled
0h = DC Coupled Input
1h = AC Coupled Input
6 RX_EN_RTERM_LSB R/W 0h Enable/Disables termination resistors on CLKIN1
0h = Disabled
1h = Enabled
5:4 RESERVED R 0h Reserved
3 PD_RESTOREB R/W 1h Save Configuration in Power Down
0h = Config Cleared
1h = Config Saved
2:1 RESERVED R 0h Reserved
0 LOSb_RB R 0h Real time read back of loss detect block output
0h = LOS Event Detected
1h = LOS Event Not-Detected

9.2.15 R20 Register (Offset = 14h) [Reset = EEh]

R20 is shown in Table 9-45.

Return to the Table 9-29.

Table 9-45 R20 Register Field Descriptions
Bit Field Type Reset Description
7 SLEWRATE_SEL_CLK2_MSB R/W 1h MSB CLK2 slew rate select
6 SLEWRATE_SEL_CLK3_MSB R/W 1h MSB CLK3 slew rate select
5 SLEWRATE_SEL_CLK4_MSB R/W 1h MSB CLK4 slew rate select
4 RESERVED R 0h Reserved
3 SLEWRATE_SEL_CLK5_MSB R/W 1h MSB CLK5 slew rate select
2 SLEWRATE_SEL_CLK6_MSB R/W 1h MSB CLK6 slew rate select
1 SLEWRATE_SEL_CLK7_MSB R/W 1h MSB CLK7 slew rate select
0 RESERVED R 0h Reserved

9.2.16 R21 Register (Offset = 15h) [Reset = 24h]

R21 is shown in Table 9-46.

Return to the Table 9-29.

Table 9-46 R21 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SLEWRATE_SEL_CLK0_MSB R/W 1h MSB CLK0 slew rate select
4:3 RESERVED R 0h Reserved
2 SLEWRATE_SEL_CLK1_MSB R/W 1h MSB CLK1 slew rate select
1:0 RESERVED R 0h Reserved

9.2.17 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 9-47.

Return to the Table 9-29.

Table 9-47 R38 Register Field Descriptions
Bit Field Type Reset Description
7:1 RESERVED R 0h Reserved
0 WRITE_LOCK R 0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

9.2.18 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 9-48.

Return to the Table 9-29.

Table 9-48 R39 Register Field Descriptions
Bit Field Type Reset Description
7:2 RESERVED R 0h Reserved
1 LOS_EVT R/W 0h LOS Event Status. When high, indicates that a LOS event is detected. Can be cleared by writing a 1.
0h = Not LOS Event Detected
1h = LOS Event Detected
0 WRITE_LOCK_RW1C R 0h Clearable SMBus Write Lock bit. When written to one, the SMBus control registers can not be written to. This bit can be cleared by writing a 1.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

9.2.19 R53 Register (Offset = 35h) [Reset = 00h]

R53 is shown in Table 9-49.

Return to the Table 9-29.

Table 9-49 R53 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SLEWRATE_CTRL_MODE R/WSC 0h Sets which mode is used to change the outputs slew rates
0h = Pin mode
1h = SMBus mode
4:0 RESERVED R 0h Reserved

9.2.20 R91 Register (Offset = 5Bh) [Reset = 60h]

R91 is shown in Table 9-50.

Return to the Table 9-29.

Table 9-50 R91 Register Field Descriptions
Bit Field Type Reset Description
7:4 SLEWRATE_OPT_2 R/W 6h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 2nd option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15
3:0 SLEWRATE_OPT_1 R/W 0h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 1st option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15

9.2.21 R92 Register (Offset = 5Ch) [Reset = FAh]

R92 is shown in Table 9-51.

Return to the Table 9-29.

Table 9-51 R92 Register Field Descriptions
Bit Field Type Reset Description
7:4 SLEWRATE_OPT_4 R/W Fh There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 4th option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15
3:0 SLEWRATE_OPT_3 R/W Ah There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 3rd option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15

9.2.22 R98 Register (Offset = 62h) [Reset = 00h]

R98 is shown in Table 9-52.

Return to the Table 9-29.

Table 9-52 R98 Register Field Descriptions
Bit Field Type Reset Description
7 SLEWRATE_SEL_CLK7_LSB R/W 0h LSB CLK7 Slew Rate Control
6 SLEWRATE_SEL_CLK6_LSB R/W 0h LSB CLK6 Slew Rate Control
5 SLEWRATE_SEL_CLK5_LSB R/W 0h LSB CLK5 Slew Rate Control
4 SLEWRATE_SEL_CLK4_LSB R/W 0h LSB CLK4 Slew Rate Control
3 SLEWRATE_SEL_CLK3_LSB R/W 0h LSB CLK3 Slew Rate Control
2 SLEWRATE_SEL_CLK2_LSB R/W 0h LSB CLK2 Slew Rate Control
1 SLEWRATE_SEL_CLK1_LSB R/W 0h LSB CLK1 Slew Rate Control
0 SLEWRATE_SEL_CLK0_LSB R/W 0h LSB CLK0 Slew Rate Control