SNAS855D November   2023  – June 2024 LMKDB1108 , LMKDB1120 , LMKDB1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Output Banks
        2. 8.3.4.2 Double Termination
        3. 8.3.4.3 Programmable Output Slew Rate
          1. 8.3.4.3.1 Slew Rate Control through Pin
          2. 8.3.4.3.2 Slew Rate Control through SMBus
        4. 8.3.4.4 Programmable Output Swing
        5. 8.3.4.5 Accurate Output Impedance
        6. 8.3.4.6 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1104 Registers
    4. 9.4 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3 LMKDB1104 Registers

Table 9-53 lists the memory-mapped registers for the LMKDB1104 registers. All register offset addresses not listed in Table 9-53 must be considered as reserved locations and the register contents must not be modified.

Table 9-53 LMKDB1104 Registers
Offset Acronym Register Name Section
0h R0 Output Enable Control for CLK2 and CLK3 Section 9.3.1
1h R1 Output Enable Control for CLK0 and CLK1 Section 9.3.2
2h R2 OE Pin Readback for CLK2 and CLK3 Section 9.3.3
3h R3 OE Pin Readback for CLK0 and CLK1 Section 9.3.4
4h R4 Readback status of SBI_EN and CLKIN AOD Enable Control Section 9.3.5
5h R5 Device Info Section 9.3.6
6h R6 Device Info (cont.) Section 9.3.7
7h R7 SMBus Byte Counter Section 9.3.8
8h R8 Mask off Side-Band Disable for CLK3 and CLK2 Section 9.3.9
9h R9 Mask off Side-Band Disable for CLK1 and CLK0 Section 9.3.10
Bh R11 Readback of Side-Band Disable for CLK3 and CLK2 Section 9.3.11
Ch R12 Readback of Side-Band Disable for CLK1 and CLK0 Section 9.3.12
11h R17 Output Amplitude Section 9.3.13
12h R18 Input Configuration, Save Config in PD, Slew Rate select mode, SMB SDATA Monitoring, and LOS Readback Section 9.3.14
14h R20 Output Slew Rate Select MSB for CLK2 and CLK3 Section 9.3.15
15h R21 Output Slew Rate Select MSB for CLK0 and CLK1 Section 9.3.16
26h R38 Non-clearable SMBUS Write Lock Section 9.3.17
27h R39 LOS Event Status and Clearable SMBus Write Lock Section 9.3.18
5Bh R91 Slew Rate Speed Options 1 and 2 Assignments Section 9.3.19
5Ch R92 Slew Rate Speed Options 3 and 4 Assignments Section 9.3.20
62h R98 Output Slew Rate Select LSB for CLK0 and CLK1 Section 9.3.21
63h R99 Output Slew Rate Select LSB for CLK2 and CLK3 Section 9.3.22

Complex bit access types are encoded to fit into small table cells. Table 9-54 shows the codes that are used for access types in this section.

Table 9-54 LMKDB1104 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W
1C		 Write
1 to clear
Reset or Default Value
-n Value after reset or the default value

9.3.1 R0 Register (Offset = 0h) [Reset = 24h]

R0 is shown in Table 9-55.

Return to the Table 9-53.

Table 9-55 R0 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 CLK_EN_2 R/W 1h Output Enable for CLK2
0h = Output Disabled (low/low)
1h = Output Enabled
4:3 RESERVED R 0h Reserved
2 CLK_EN_3 R/W 1h Output Enable for CLK3
0h = Output Disabled (low/low)
1h = Output Enabled
1:0 RESERVED R 0h Reserved

9.3.2 R1 Register (Offset = 1h) [Reset = 22h]

R1 is shown in Table 9-56.

Return to the Table 9-53.

Table 9-56 R1 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 CLK_EN_0 R/W 1h Output Enable for CLK0
0h = Output Disabled (low/low)
1h = Output Enabled
4:2 RESERVED R 0h Reserved
1 CLK_EN_1 R/W 1h Output Enable for CLK1
0h = Output Disabled (low/low)
1h = Output Enabled
0 RESERVED R 0h Reserved

9.3.3 R2 Register (Offset = 2h) [Reset = 00h]

R2 is shown in Table 9-57.

Return to the Table 9-53.

Table 9-57 R2 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 RB_OEb_2 R 0h Status of OEb2
4:3 RESERVED R 0h Reserved
2 RB_OEb_3 R 0h Status of OEb3
1:0 RESERVED R 0h Reserved

9.3.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 9-58.

Return to the Table 9-53.

Table 9-58 R3 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 RB_OEb_0 R 0h Status of OEb0
4:2 RESERVED R 0h Reserved
1 RB_OEb_1 R 0h Status of OEb1
0 RESERVED R 0h Reserved

9.3.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 9-59.

Return to the Table 9-53.

Table 9-59 R4 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4 AOD_ENABLE R/W 1h Enable automatic output disable (AOD) for CLKIN to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Inactive
1h = Active
3:1 RESERVED R 0h Reserved
0 RB_SBI_ENQ R 0h Status of SBI_ENQ

9.3.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 9-60.

Return to the Table 9-53.

Table 9-60 R5 Register Field Descriptions
Bit Field Type Reset Description
7:4 REV_ID R 0h Revision ID
3:0 VENDOR_ID R Ah Vendor ID

9.3.7 R6 Register (Offset = 6h) [Reset = 04h]

R6 is shown in Table 9-61.

Return to the Table 9-53.

Table 9-61 R6 Register Field Descriptions
Bit Field Type Reset Description
7:0 DEV_ID R 4h Device ID

9.3.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 9-62.

Return to the Table 9-53.

Table 9-62 R7 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4:0 SMBUS_BC R/W 7h SMBUS Block Read Byte Count

9.3.9 R8 Register (Offset = 8h) [Reset = 00h]

R8 is shown in Table 9-63.

Return to the Table 9-53.

Table 9-63 R8 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SBI_MASK_2 R/W 0h Mask off Side-Band Disable for CLK2
4:3 RESERVED R 0h Reserved
2 SBI_MASK_3 R/W 0h Mask off Side-Band Disable for CLK3
1:0 RESERVED R 0h Reserved

9.3.10 R9 Register (Offset = 9h) [Reset = 00h]

R9 is shown in Table 9-64.

Return to the Table 9-53.

Table 9-64 R9 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SBI_MASK_0 R/W 0h Mask off Side-Band Disable for CLK0
4:2 RESERVED R 0h Reserved
1 SBI_MASK_1 R/W 0h Mask off Side-Band Disable for CLK1
0 RESERVED R 0h Reserved

9.3.11 R11 Register (Offset = Bh) [Reset = 24h]

R11 is shown in Table 9-65.

Return to the Table 9-53.

Table 9-65 R11 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SBI_CLK_2 R 1h Readback of Side-Band Disable for CLK2
4:3 RESERVED R 0h Reserved
2 SBI_CLK_3 R 1h Readback of Side-Band Disable for CLK3
1:0 RESERVED R 0h Reserved

9.3.12 R12 Register (Offset = Ch) [Reset = 22h]

R12 is shown in Table 9-66.

Return to the Table 9-53.

Table 9-66 R12 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SBI_CLK_0 R 1h Readback of Side-Band Disable for CLK0
4:2 RESERVED R 0h Reserved
1 SBI_CLK_1 R 1h Readback of Side-Band Disable for CLK1
0 RESERVED R 0h Reserved

9.3.13 R17 Register (Offset = 11h) [Reset = 66h]

R17 is shown in Table 9-67.

Return to the Table 9-53.

Table 9-67 R17 Register Field Descriptions
Bit Field Type Reset Description
7:4 AMP R/W 6h Global Differential output Control,approximately 0.6V to 1V 25mV/step (default = 0.75V)
0h = 600 mV
1h = 625 mV
2h = 650 mV
3h = 675 mV
4h = 700 mV
5h = 725 mV
6h = 750 mV
7h = 775 mV
8h = 800 mV
9h = 825 mV
Ah = 850 mV
Bh = 875 mV
Ch = 900 mV
Dh = 925 mV
Eh = 950 mV
Fh = 975 mV
3:0 RESERVED R 0h Reserved

9.3.14 R18 Register (Offset = 12h) [Reset = 0Ah]

R18 is shown in Table 9-68.

Return to the Table 9-53.

Table 9-68 R18 Register Field Descriptions
Bit Field Type Reset Description
7 RX_CLKIN_EN_AC_INPUT R/W 0h Enable receiver bias when CLKIN is AC coupled
0h = DC Coupled Input
1h = AC Coupled Input
6 RX_CLKIN_EN_RTERM R/W 0h Enable termination resistors on CLKIN1
0h = Input termination inactive
1h = Input termination active
5 RESERVED R 0h Reserved
4 SLEWRATE_CTRL_MODE R 0h Slew rate select preference between pin mode and register mode.
0h = Pin Control
1h = Register Control
3 PD_RESTOREB R 1h Save configuration in powerdown
0h = Config Cleared
1h = Config Saved
2 RESERVED R 0h Reserved
1 SDATA_TIMEOUT_EN R 1h Enable SMBus SDATA time out monitoring
0h = Disable SDATA timeout
1h = Enable SDATA timeout
0 LOSb_RB R 0h Real time read back of loss detect block output
0h = LOS Event Detected
1h = LOS Event Not-Detected

9.3.15 R20 Register (Offset = 14h) [Reset = 24h]

R20 is shown in Table 9-69.

Return to the Table 9-53.

Table 9-69 R20 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SLEWRATE_SEL_CLK2_MSB R/W 1h MSB CLK2 slew rate select
4:3 RESERVED R 0h Reserved
2 SLEWRATE_SEL_CLK3_MSB R/W 1h MSB CLK3 slew rate select
1:0 RESERVED R 0h Reserved

9.3.16 R21 Register (Offset = 15h) [Reset = 22h]

R21 is shown in Table 9-70.

Return to the Table 9-53.

Table 9-70 R21 Register Field Descriptions
Bit Field Type Reset Description
7:6 RESERVED R 0h Reserved
5 SLEWRATE_SEL_CLK0_MSB R/W 1h MSB CLK0 slew rate select
4:2 RESERVED R 0h Reserved
1 SLEWRATE_SEL_CLK1_MSB R/W 1h MSB CLK1 slew rate select
0 RESERVED R 0h Reserved

9.3.17 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 9-71.

Return to the Table 9-53.

Table 9-71 R38 Register Field Descriptions
Bit Field Type Reset Description
7:1 RESERVED R 0h Reserved
0 WRITE_LOCK R 0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

9.3.18 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 9-72.

Return to the Table 9-53.

Table 9-72 R39 Register Field Descriptions
Bit Field Type Reset Description
7:2 RESERVED R 0h Reserved
1 LOS_EVT R 0h LOS Event Status. When high, indicates that a LOS event is detected. Can be cleared by writing a 1.
0h = Not LOS Event Detected
1h = LOS Event Detected
0 WRITE_LOCK_RW1C R/W1C 0h Clearable SMBus Write Lock bit. When written to one, the SMBus control registers can not be written to. This bit can be cleared by writing a 1.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

9.3.19 R91 Register (Offset = 5Bh) [Reset = 60h]

R91 is shown in Table 9-73.

Return to the Table 9-53.

Table 9-73 R91 Register Field Descriptions
Bit Field Type Reset Description
7:4 SLEWRATE_OPT_2 R/W 6h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 2nd option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
3:0 SLEWRATE_OPT_1 R/W 0h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 1st option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)

9.3.20 R92 Register (Offset = 5Ch) [Reset = FAh]

R92 is shown in Table 9-74.

Return to the Table 9-53.

Table 9-74 R92 Register Field Descriptions
Bit Field Type Reset Description
7:4 SLEWRATE_OPT_4 R/W Fh There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 4th option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
3:0 SLEWRATE_OPT_3 R/W Ah There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 3rd option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)

9.3.21 R98 Register (Offset = 62h) [Reset = 00h]

R98 is shown in Table 9-75.

Return to the Table 9-53.

Table 9-75 R98 Register Field Descriptions
Bit Field Type Reset Description
7 SLEWRATE_SEL_CLK1_LSB R/W 0h LSB CLK1 Slew Rate Control
6:5 RESERVED R 0h Reserved
4 SLEWRATE_SEL_CLK0_LSB R/W 0h LSB CLK0 Slew Rate Control
3:0 RESERVED R 0h Reserved

9.3.22 R99 Register (Offset = 63h) [Reset = 00h]

R99 is shown in Table 9-76.

Return to the Table 9-53.

Table 9-76 R99 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0h Reserved
6 SLEWRATE_SEL_CLK3_LSB R/W 0h LSB CLK3 Slew Rate Control
5:3 RESERVED R 0h Reserved
2 SLEWRATE_SEL_CLK2_LSB R/W 0h LSB CLK2 Slew Rate Control
1:0 RESERVED R 0h Reserved