SNAS855D November   2023  – June 2024 LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Output Banks
        2. 8.3.4.2 Double Termination
        3. 8.3.4.3 Programmable Output Slew Rate
          1. 8.3.4.3.1 Slew Rate Control through Pin
          2. 8.3.4.3.2 Slew Rate Control through SMBus
        4. 8.3.4.4 Programmable Output Swing
        5. 8.3.4.5 Accurate Output Impedance
        6. 8.3.4.6 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1104 Registers
    4. 9.4 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions



Figure 5-1 LMKDB1120 NPP Package, 80-Pin TLGA (Top View)
Table 5-1 LMKDB1120 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CLKIN_P G1 I Differential clock input.
CLKIN_N H1 I
CLK0_P J1 O LP-HCSL differential clock output 0. No connect if unused.
CLK0_N K1 O
CLK1_P L1 O LP-HCSL differential clock output 1. No connect if unused.
CLK1_N M1 O
CLK2_P M2 O LP-HCSL differential clock output 2. No connect if unused.
CLK2_N M3 O
CLK3_P M4 O LP-HCSL differential clock output 3. No connect if unused.
CLK3_N M5 O
CLK4_P M7 O LP-HCSL differential clock output 4. No connect if unused.
CLK4_N M8 O
CLK5_P M9 O LP-HCSL differential clock output 5. No connect if unused.
CLK5_N M10 O
CLK6_P M11 O LP-HCSL differential clock output 6. No connect if unused.
CLK6_N M12 O
CLK7_P L12 O LP-HCSL differential clock output 7. No connect if unused.
CLK7_N K12 O
CLK8_P J12 O LP-HCSL differential clock output 8. No connect if unused.
CLK8_N H12 O
CLK9_P G12 O LP-HCSL differential clock output 9. No connect if unused.
CLK9_N F12 O
CLK10_P D12 O LP-HCSL differential clock output 10. No connect if unused.
CLK10_N C12 O
CLK11_P B12 O LP-HCSL differential clock output 11. No connect if unused.
CLK11_N A12 O
CLK12_P A11 O LP-HCSL differential clock output 12. No connect if unused.
CLK12_N A10 O
CLK13_P A9 O LP-HCSL differential clock output 13. No connect if unused.
CLK13_N A8 O
CLK14_P A7 O LP-HCSL differential clock output 14. No connect if unused.
CLK14_N A6 O
CLK15_P A5 O LP-HCSL differential clock output15. No connect if unused.
CLK15_N A4 O
CLK16_P A3 O LP-HCSL differential clock output 16. No connect if unused.
CLK16_N A2 O
CLK17_P A1 O LP-HCSL differential clock output 17. No connect if unused.
CLK17_N B1 O
CLK18_P C1 O LP-HCSL differential clock output 18. No connect if unused.
CLK18_N D1 O
CLK19_P E1 O LP-HCSL differential clock output 19. No connect if unused.
CLK19_N F1 O
DAP GND G Ground. Thermal Pad
LOS#/NC G11 O Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor. This pin can be left no connect to match with DB2000QL pinout.
  • Low = Invalid input clock.
  • High = Valid input clock.
NC F2 NC No Connect
NC F11 NC No Connect
NC G2 NC No Connect
NC L7 NC No Connect
SBI_OUT/NC C2 O SBI Data Output/No Connect. This pin can be left no connect to match with DB2000QL pinout.
SMB_DATA L4 I/O SMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK L5 I SMBus Clock. Requires external pullup resistor. No connect if unused.
VDDA H2 P Analog power supply. Additional power supply filtering is recommended. See Power Supply Recommendations for details.
VDD B2 P Power supply.
VDD B6 P Power supply.
VDD B11 P Power supply.
VDD L2 P Power supply.
VDD L11 P Power supply.
vOE0#/NC J2 I Output Enable for CLK0 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE1#/NC K2 I Output Enable for CLK1 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE2#/NC L3 I Output Enable for CLK2 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE3#/NC L6 I Output Enable for CLK3 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE4#/NC L9 I Output Enable for CLK4 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE5#/SBI_IN L8 I Output Enable for CLK5 Active Low/SBI Data Input. Internal pulldown resistor. Functionality is decided by the state of pin E2 (SBI_EN) at power-up. No connect if unused.
vOE6#/SBI_CLK L10 I Output Enable for CLK6 Active Low/SBI Clock. Internal pulldown resistor. Functionality is decided by the state of pin E2 (SBI_EN) at power-up. Internal pulldown resistor. No connect if unused.
vOE7# K11 I Output Enable for CLK7 Active Low. Internal pulldown resistor. No connect if unused.
vOE8# H11 I Output Enable for CLK8 Active Low. Internal pulldown resistor. No connect if unused.
vOE9# E12 I Output Enable for CLK9 Active Low. Internal pulldown resistor. No connect if unused.
vOE10#/SHFT_LD# E11 I Output Enable for CLK10 Active Low/SBI Shift Register Load Active Low. Internal pulldown resistor. Functionality is decided by the state of pin E2 (SBI_EN) at power-up. No connect if unused.
vOE11# C11 I Output Enable for CLK11 Active Low. Internal pulldown resistor. No connect if unused.
vOE12# B10 I Output Enable for CLK12 Active Low. Internal pulldown resistor. No connect if unused.
vOE13#/NC B9 I Output Enable for CLK13 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE14#/NC B7 I Output Enable for CLK14 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE15#/NC B5 I Output Enable for CLK15 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE16#/NC B3 I Output Enable for CLK16 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE17#/NC D2 I Output Enable for CLK17 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE18#/NC D11 I Output Enable for CLK18 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vOE19#/NC J11 I Output Enable for CLK19 Active Low/No Connect. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.
vPWRGD/PWRDN# M6 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.
  • On the first low-to-high transition, functions as Power Good pin which starts up the device
  • On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.
    • Low = power-down mode
    • High = normal operation mode
vSBI_EN E2 I SBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.
  • Low at power-up = SBI interface disabled. Pin L8, L10, E11 function as OE pins.
  • High at power-up = SBI interface enabled. Pin L8, L10, E11 function as SBI interface pins. SMBus and other OE pins remain functional.
^vSADR1_tri B8 I SMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_tri B4 I SMBus Address 3-level input pin. Internal pullup and pulldown resistors.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
Figure 5-2 LMKDB1108 RKP Package, 40-Pin VQFN (Top View)

Table 5-2 LMKDB1108 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CLKIN_P 8 I Differential clock input.
CLKIN_N 9 I
CLK0_P 15 O LP-HCSL differential clock output 0. No connect if unused.
CLK0_N 16 O
CLK1_P 17 O LP-HCSL differential clock output 1. No connect if unused.
CLK1_N 18 O
CLK2_P 22 O LP-HCSL differential clock output 2. No connect if unused.
CLK2_N 23 O
CLK3_P 24 O LP-HCSL differential clock output 3. No connect if unused.
CLK3_N 25 O
CLK4_P 28 O LP-HCSL differential clock output 4. No connect if unused.
CLK4_N 29 O
CLK5_P 31 O LP-HCSL differential clock output 5. No connect if unused.
CLK5_N 32 O
CLK6_P 35 O LP-HCSL differential clock output 6. No connect if unused.
CLK6_N 36 O
CLK7_P 38 O LP-HCSL differential clock output 7. No connect if unused.
CLK7_N 39 O
vPWRGD/PWRDN# 12 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.
  • On the first low-to-high transition, functions as Power Good pin which starts up the device
  • On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.
    • Low = power-down mode
    • High = normal operation mode
vOE0#/SHFT_LD# 14 I Output Enable for CLK0 Active Low/SBI Shift Register Load Active Low. Internal pulldown resistor. Functionality is decided by the state of pin 11 (SBI_EN) at power-up. No connect if unused.
vOE1#/SBI_IN 19 I Output Enable for CLK1 Active Low/SBI Data Input. Internal pulldown resistor. Functionality is decided by the state of pin 11 (SBI_EN) at power-up. No connect if unused.
vOE2# 21 I Output Enable for CLK2 Active Low. Internal pulldown resistor. No connect if unused.
vOE3# 27 I Output Enable for CLK3 Active Low. Internal pulldown resistor. No connect if unused.
vOE4#/SBI_CLK 30 I Output Enable for CLK4 Active Low/SBI Clock. Internal pulldown resistor. Functionality is decided by the state of pin 11 (SBI_EN) at power-up. Internal pulldown resistor. No connect if unused.
vOE5# 33 I Output Enable for CLK5 Active Low. Internal pulldown resistor. No connect if unused.
vOE6#/SBI_OUT 34 I or O Output Enable for CLK6 Active Low/SBI Data Output. Functionality is decided by the state of pin 11 (SBI_EN) at power-up. Internal pulldown resistor. No connect if unused.
vOE7# 40 I Output Enable for CLK7 Active Low. Internal pulldown resistor. No connect if unused.
vSBI_EN 11 I SBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.
  • Low at power-up = SBI interface disabled. Pin 14, 19, 30, 34 function as OE pins.
  • High at power-up = SBI interface enabled. Pin 14, 19, 30, 34 function as SBI interface pins. SMBus and other OE pins remain functional.
SMB_DATA 5 I/O SMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK 6 I SMBus Clock. Requires external pullup resistor. No connect if unused.
^vSADR1_tri 3 I SMBus Address 3-level input pins. These two pins select 1 out of 9 SMBus addresses.
^vSADR0_tri 4 I SMBus Address 3-level input pins. These two pins select 1 out of 9 SMBus addresses.
^SLEWRATE_SEL 2 I Slew Rate Select for output clocks. Internal pullup resistor.
  • Low = Slow slew rate
  • High = Fast slew rate
LOS# 1 O Loss of Input Clock Signal Active Low. Open drain. Requires external pullup resistor.
  • Low = Invalid input clock.
  • High = Valid input clock.
VDDA 7 P Analog power supply. Additional power supply filtering is recommended. See Power Supply Recommendations for details.
VDD 13 P Power supply.
VDD 20 P Power supply.
VDD 26 P Power supply.
VDD 37 P Power supply.
VDD 10 P Power supply.
DAP GND G Ground.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
Figure 5-3 LMKDB1104 4 x 4 mm 28-pin QFN
Table 5-3 LMKDB1104 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CLKIN_P 6 I Differential clock input
CLKIN_N 7 I
CLK0_P 12 O LP-HCSL differential clock output 0
CLK0_N 13 O
CLK1_P 16 O LP-HCSL differential clock output 1
CLK1_N 17 O
CLK2_P 19 O LP-HCSL differential clock output 2
CLK2_N 20 O
CLK3_P 23 O LP-HCSL differential clock output 3
CLK3_N 24 O
vPWRGD/PWRDN# 9 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.
  • On the first low-to-high transition, functions as Power Good pin which starts up the device
  • On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.
    • Low = power-down mode
    • High = normal operation mode
vOE0#/SHFT_LD# 11 I Output Enable for CLK0 Active Low/SBI Shift Register Load Active Low. Internal pulldown resistor. Functionality is decided by the state of pin 8 (SBI_EN) at power-up. No connect if unused.
vOE1#/SBI_IN 14 I Output Enable for CLK1 Active Low/SBI Data Input. Internal pulldown resistor. Functionality is decided by the state of pin 8 (SBI_EN) at power-up. No connect if unused.
vOE2#/SBI_CLK 21 I Output Enable for CLK2 Active Low/SBI Clock. Internal pulldown resistor. Functionality is decided by the state of pin 8 (SBI_EN) at power-up. Internal pulldown resistor. No connect if unused.
vOE3#/SBI_OUT 22 I or O Output Enable for CLK3 Active Low/SBI Data Output. Internal pulldown resistor. Functionality is decided by the state of pin 8 (SBI_EN) at power-up. Internal pulldown resistor. No connect if unused.
vSBI_EN 8 I SBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.
  • Low at power-up = SBI interface disabled. Pin 11, 14, 21, 22 function as OE pins.
  • High at power-up = SBI interface enabled. Pin 11, 14, 21, 22 function as SBI interface pins. SMBus and other OE pins remain functional.
SMB_DATA 3 I/O SMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK 4 I SMBus Clock. Requires external pullup resistor. No connect if unused.
^vSADR1_tri 1 I SMBus Address 3-level input pins. These two pins select 1 out of 9 SMBus addresses.
^vSADR0_tri 2 I SMBus Address 3-level input pins. These two pins select 1 out of 9 SMBus addresses.
^SLEWRATE_SEL 27 I Slew Rate Select for output clocks. Internal pullup resistor.
  • Low = Slow slew rate
  • High = Fast slew rate
LOS# 28 O Loss of Input Clock Signal Active Low. Open drain. Requires external pullup resistor.
  • Low = Invalid input clock.
  • High = Valid input clock.
VDDA 5 P Analog power supply. Additional power supply filtering is recommended. See Power Supply Recommendations for details.
VDD 10, 15, 18, 25 P Power supply.
GND DAP G Ground.
NC 26 NC No Connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
Figure 5-4 LMKDB1204 4 x 4 mm 28-pin QFN
Table 5-4 LMKDB1204 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CLKIN0_P 2 I Differential clock input 0
CLKIN0_N 3 I
CLKIN1_P 5 I Differential clock input 1
CLKIN1_N 6 I
CLK3_P 10 O LP-HCSL differential clock output 3. Output Bank 1.
CLK3_N 11 O
CLK2_P 13 O LP-HCSL differential clock output 2. Output Bank 1.
CLK2_N 14 O
CLK1_P 20 O LP-HCSL differential clock output 1. Output Bank 0.
CLK1_N 21 O
CLK0_P 23 O LP-HCSL differential clock output 0. Output Bank 0.
CLK0_N 24 O
vPWRGD/PWRDN# 1 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.
  • On the first low-to-high transition, functions as Power Good pin which starts up the device
  • On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.
    • Low = power-down mode
    • High = normal operation mode
^OE3#/SMB_CLK 9 I Output Enable for CLK3 Active Low/SMBus Clock. Internal pullup resistor. Functionality is decided by the state of pin 15 (SMB_EN) at power-up. When used as SMBus Clock pin, external pullup resistor is required. No connect if unused.
^OE2# 16 I Output Enable for CLK2 Active Low. Internal pullup resistor. No connect if unused.
^OE1# 19 I Output Enable for CLK1 Active Low. Internal pullup resistor. No connect if unused.
^OE0# 25 I Output Enable for CLK0 Active Low. Internal pullup resistor. No connect if unused.
^vCLKIN_SEL_tri/SMB_DATA 8 I or I/O 3-Level Clock Input Select/SMBus Data. Internal pullup and pulldown resistor. Functionality is decided by the state of pin 15 (SMB_EN) at power-up.
  • When used as CLKIN_SEL_tri pin:
    • Low = CLKIN0 goes to all outputs
    • Mid = CLKIN0 goes to Bank 0, CLKIN1 goes to Bank 1
    • High = CLKIN1 goes to all outputs
  • When used as SMBus Data pin, external pullup resistor is required.
vSMB_EN 15 I SMBus Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.
  • Low at power-up = SMBus disabled. Pin 8 is CLKIN_SEL_tri and Pin 9 is OE3#.
  • High at power-up = SMBus enabled. Pin 8 is SMB_DATA and Pin 9 is SMB_CLK.
vZOUT_SEL 28 I LP-HCSL Differential Clock Output Impedance Select. Internal pulldown resistor.
  • Low = 85Ω
  • High = 100Ω
LOS# 17 O Loss of Input Clock Signal Active Low. Open drain. Requires external pullup resistor.
  • Low = Invalid input clock.
  • High = Valid input clock.
VDD_IN0 4 P Power supply for CLKIN0.
VDD_IN1 7 P Power supply for CLKIN1.
VDDO_BANK1 12 P Power supply for output bank 1 (OUT2 and OUT3)
VDDO_BANK0 22 P Power supply for output bank 0 (OUT0 and OUT1)
VDD_DIG 26 P Power supply for digital
VDDA 18 P Analog power supply. Additional power supply filtering is recommended. See Power Supply Recommendations for details.
GND 27, DAP G Ground.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
Figure 5-5 LMKDB1202 3 x 3 mm 20-pin QFN
Table 5-5 LMKDB1202 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CLKIN0_P, CLKIN0_N 1, 2 I Differential clock input 0
CLKIN1_P, CLKIN1_N 4, 5 I Differential clock input 1
CLK2_P, CLK2_N 9, 10 O LP-HCSL differential clock output 2. Output Bank 1.
CLK1_P, CLK1_N 16, 17 O LP-HCSL differential clock output 1. Output Bank 0.
^OE2# 12 I Output Enable for CLK2 Active Low. Internal pullup resistor. No connect if unused.
^OE1# 15 I Output Enable for CLK1 Active Low. Internal pullup resistor. No connect if unused. This pin requires either of below conditions to dynamically enable or disable the CLK1 after power-up. If CLK1 stays enabled or disabled after power-up, then below conditions do not need to be met.
  • This pin is driven low or high at ≥0.1 V/ns slew rate.
  • The resistance used to drive this pin is ≤1 kΩ.

The above requirement is only needed for Pin 15.
^vCLKIN_SEL_tri 7 I 3-Level Clock Input Select
  • Low = CLKIN0 goes to all outputs
  • Mid = CLKIN0 goes to Bank 0, CLKIN1 goes to Bank 1
  • High = CLKIN1 goes to all outputs
vZOUT_SEL 11 I LP-HCSL Differential Clock Output Impedance Select. Internal pulldown resistor.
  • Low = 85Ω
  • High = 100Ω
LOS# 13 O Loss of Input Clock Signal Active Low. Open drain. Requires external pullup resistor.
  • Low = Invalid input clock.
  • High = Valid input clock.
VDD_IN0 3 P Power supply for CLKIN0
VDD_IN1 6 P Power supply for CLKIN1
VDDO_BANK1 8 P Power supply for output bank 1 (CLK2)
VDD 14 P Power supply
VDDO_BANK0 18 P Power supply for output bank 0 (CLK1)
VDD_DIG 19 P Power supply for digital
GND 20, DAP G Ground.
Figure 5-6 LMKDB1102 3 x 3 mm 20-pin QFN
Table 5-6 LMKDB1102 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CLKIN_P, 1 I Differential clock input
CLKIN_N 2 I Differential clock input
NC 4, 5 I No connect. Leave floating
CLK2_P 9 O LP-HCSL differential clock output 2
CLK2_N 10 O LP-HCSL differential clock output 2
CLK1_P 16 O LP-HCSL differential clock output 1
CLK1_N 17 O LP-HCSL differential clock output 1
^OE2# 12 I Output Enable for CLK2 Active Low. Internal pullup resistor. No connect if unused.
^OE1# 15 I Output Enable for CLK1 Active Low. Internal pullup resistor. No connect if unused. This pin requires either of below conditions to dynamically enable or disable the CLK1 after power-up. If CLK1 stays enabled or disabled after power-up, then below conditions do not need to be met.
  • This pin is driven low or high at ≥0.1 V/ns slew rate.
  • The resistance used to drive this pin is ≤1 kΩ.

The above requirement is only needed for Pin 15.
GND 7 I or GND Digital 0 or GND. Tie to GND through pull down resistor or directly tie to GND.
vZOUT_SEL 11 I LP-HCSL Differential Clock Output Impedance Select. Internal pulldown resistor.
  • Low = 85 Ω
  • High = 100 Ω
LOS# 13 O Loss of Input Clock Signal Active Low. Open drain. Requires external pullup resistor.
  • Low = Invalid input clock.
  • High = Valid input clock.
VDDA 6 P Analog power supply. Additional power supply filtering is recommended. See Power Supply Recommendations for details.
VDD 3, 8, 14, 18, 19 P Power supply
GND 20, DAP G Ground.