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  • LMP2011 Single/LMP2012 Dual High Precision, Rail-to-Rail Output Operational Amplifier

    • SNOSA71L October   2004  – September 2015 LMP2011 , LMP2012

      PRODUCTION DATA.  

  • CONTENTS
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  • LMP2011 Single/LMP2012 Dual High Precision, Rail-to-Rail Output Operational Amplifier
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: LMP2011
    5. 6.5  Thermal Information: LMP2012
    6. 6.6  2.7-V DC Electrical Characteristics
    7. 6.7  2.7-V AC Electrical Characteristics
    8. 6.8  5-V DC Electrical Characteristics
    9. 6.9  5-V AC Electrical Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 How the LMP201x Works
      2. 7.3.2 The Benefits of LMP201x: No 1/F Noise
      3. 7.3.3 No External Capacitors Required
      4. 7.3.4 Copper Leadframe
      5. 7.3.5 More Benefits
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Currents
      2. 7.4.2 Overload Recovery
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Extending Supply Voltages and Output Swing with a Composite Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Results
      2. 8.2.2 Precision Strain-gauge Amplifier
      3. 8.2.3 ADC Input Amplifier
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • D|8
    • MSOI002K
  • DGK|8
    • MPDS028E
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • snosa71l_oa
  • snosa71l_pm
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DATA SHEET

LMP2011 Single/LMP2012 Dual High Precision, Rail-to-Rail Output Operational Amplifier

1 Features

    (For VS = 5 V, Typical Unless Otherwise Noted)

  • Low Ensured VOS Over Temperature 60 µV
  • Low Noise with No 1/f 35nV/√Hz
  • High CMRR 130 dB
  • High PSRR 120 dB
  • High AVOL 130 dB
  • Wide Gain-Bandwidth Product 3 MHz
  • High Slew Rate 4 V/µs
  • Low Supply Current 930 µA
  • Rail-to-Rail Output 30 mV
  • No External Capacitors Required

2 Applications

  • Precision Instrumentation Amplifiers
  • Thermocouple Amplifiers
  • Strain Gauge Bridge Amplifier

3 Description

The LMP201x series are the first members of TI's new LMP™ precision amplifier family. The LMP201x series offers unprecedented accuracy and stability in space-saving miniature packaging, offered at an affordable price. This device utilizes patented auto-zero techniques to measure and continually correct the input offset error voltage. The result is an amplifier which is ultra-stable over time and temperature. It has excellent CMRR and PSRR ratings, and does not exhibit the familiar 1/f voltage and current noise increase that plagues traditional amplifiers. The combination of the LMP201x characteristics makes it a good choice for transducer amplifiers, high gain configurations, ADC buffer amplifiers, DAC I-V conversion, and any other 2.7-V to 5-V application requiring precision and long term stability.

Other useful benefits of the LMP201x are rail-to-rail output, a low supply current of 930 µA, and wide gain-bandwidth product of 3 MHz. These versatile features found in the LMP201x provide high performance and ease of use.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMP2011 SOIC (8) 4.90 mm × 3.91 mm
SOT-23 (5) 2.90 mm × 1.60 mm
LMP2012 SOIC (8) 4.90 mm × 3.91 mm
VSSOP (8) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Bridge Amplifier

LMP2011 LMP2012 20071518.gif

Offset Voltage vs Common Mode Voltage

LMP2011 LMP2012 20071557.gif

4 Revision History

Changes from K Revision (March 2013) to L Revision

  • Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from J Revision (March 2013) to K Revision

  • Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23 Single
Top View
LMP2011 LMP2012 20071502.png
D Package
8-Pin Single SOIC
Top View
LMP2011 LMP2012 20071542.gif

Pin Functions: LMP2011

PIN I/O DESCRIPTION
NAME NO.
DBV D
-IN 4 3 O Inverting input
+IN 3 2 I Non-Inverting input
N/C - 1 - No Internal Connection
N/C - 5 - No Internal Connection
N/C - 8 - No Internal Connection
OUT 1 6 I Output
V- 2 4 P Negative (lowest) power supply
V+ 5 7 P Positive (highest) power supply
D or DGK Package
8-Pin Dual SOIC and VSSOP
Top View
LMP2011 LMP2012 20071538.png

Pin Functions: LMP2012

PIN I/O DESCRIPTION
NAME NO.
D, DGK
–IN A 2 I Inverting input, channel A
+IN A 3 I Non-Inverting input, channel A
–IN B 6 I Inverting input, channel B
+IN B 5 I Non-Inverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V– 4 P Negative (lowest) power supply
V+ 8 P Positive (highest) power supply

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)
MIN MAX UNIT
Supply Voltage 5.8 V
Common-Mode Input Voltage (V-) - 0.3 (V+) + 0.3 V
Lead Temperature (soldering 10 sec.) 300 °C
Differential Input Voltage ±Supply Voltage
Current at Input Pin 30 30 mA
Current at Output Pin 30 30 mA
Current at Power Supply Pin 50 30 mA
Storage Temperature −65 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Machine model ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
Supply Voltage 2.7 5.25 V
Operating Temperature Range −40 125 °C

6.4 Thermal Information: LMP2011

THERMAL METRIC(1) LMP2011 UNIT
D (SOIC) DBV (SOT-23)
8 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 119 164 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66 116 °C/W
RθJB Junction-to-board thermal resistance 60 28 °C/W
ψJT Junction-to-top characterization parameter 17 13 °C/W
ψJB Junction-to-board characterization parameter 59 27 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information: LMP2012

THERMAL METRIC(1) LMP2012 UNIT
D (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 110 157 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50 51 °C/W
RθJB Junction-to-board thermal resistance 52 77 °C/W
ψJT Junction-to-top characterization parameter 8 5 °C/W
ψJB Junction-to-board characterization parameter 51 75 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 2.7-V DC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, V CM = 1.35 V, VO = 1.35 V, and RL > 1 MΩ.
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX(2) UNIT
VOS Input Offset Voltage
(LMP2011 only)		 TJ = 25°C 0.8 25 μV
The temperature extremes 60
Input Offset Voltage
(LMP2012 only)		 TJ = 25°C 0.8 36
The temperature extremes 60
Offset Calibration Time TJ = 25°C 0.5 10 ms
The temperature extremes 12
TCVOS Input Offset Voltage 0.015 μV/°C
Long-Term Offset Drift 0.006 μV/month
Lifetime VOS Drift 2.5 μV
IIN Input Current -3 pA
IOS Input Offset Current 6 pA
RIND Input Differential Resistance 9 MΩ
CMRR Common Mode Rejection Ratio −0.3 ≤ VCM ≤ 0.9 V,
0 ≤ VCM ≤ 0.9 V		 TJ = 25°C 95 130 dB
The temperature extremes 90
PSRR Power Supply Rejection Ratio TJ = 25°C 95 120 dB
The temperature extremes 90
AVOL Open Loop Voltage Gain RL = 10 kΩ TJ = 25°C 95 130 dB
The temperature extremes 90
RL = 2 kΩ TJ = 25°C 90 124
The temperature extremes 85
VO Output Swing
(LMP2011 only)		 RL = 10 kΩ to 1.35 V,
VIN(diff) = ±0.5 V 		TJ = 25°C 2.665 2.68 V
The temperature extremes 2.655
TJ = 25°C 0.033 0.060
The temperature extremes 0.075
RL = 2 kΩ to 1.35 V,
VIN(diff) = ±0.5 V		 TJ = 25°C 2.630 2.65 V
The temperature extremes 2.615
TJ = 25°C 0.061 0.085
The temperature extremes 0.105
Output Swing
(LMP2012 only) 		RL = 10 kΩ to 1.35 V,
VIN(diff) = ±0.5 V 		TJ = 25°C 2.64 2.68 V
The temperature extremes 2.63
TJ = 25°C 0.033 0.060
The temperature extremes 0.075
RL = 2 kΩ to 1.35 V,
VIN(diff) = ±0.5 V 		TJ = 25°C 2.615 2.65 V
The temperature extremes 2.6
TJ = 25°C 0.061 0.085
The temperature extremes 0.105
IO Output Current Sourcing, VO = 0 V,
VIN(diff) = ±0.5 V		 TJ = 25°C 5 12 mA
The temperature extremes 3
VIN(diff) = ±0.5 V,
Sinking, VO = 5 V 		TJ = 25°C 5 18
The temperature extremes 3
IS Supply Current per Channel TJ = 25°C 0.919 1.20 mA
The temperature extremes 1.50
(1) Typical values represent the most likely parametric norm.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.

6.7 2.7-V AC Electrical Characteristics

TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 1.35 V, VO = 1.35 V, and RL > 1 MΩ.
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX(2) UNIT
GBW Gain-Bandwidth Product 3 MHz
SR Slew Rate 4 V/μs
θ m Phase Margin 60 Deg
Gm Gain Margin −14 dB
en Input-Referred Voltage Noise 35 nV/√Hz
enp-p Input-Referred Voltage Noise RS = 100 Ω, DC to 10 Hz 850 nVpp
trec Input Overload Recovery Time 50 ms
(1) Typical values represent the most likely parametric norm.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.

6.8 5-V DC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V, V CM = 2.5 V, VO = 2.5 V, and RL > 1MΩ.
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX(2) UNIT
VOS Input Offset Voltage
(LMP2011 only)		 TJ = 25°C 0.12 25 μV
The temperature extremes 60
Input Offset Voltage
(LMP2012 only)		 TJ = 25°C 0.12 36
The temperature extremes 60
Offset Calibration Time TJ = 25°C 0.5 10 ms
The temperature extremes 12
TCVOS Input Offset Voltage 0.015 μV/°C
Long-Term Offset Drift 0.006 μV/month
Lifetime VOS Drift 2.5 μV
IIN Input Current -3 pA
IOS Input Offset Current 6 pA
RIND Input Differential Resistance 9 MΩ
CMRR Common Mode Rejection Ratio −0.3 ≤ VCM ≤ 3.2,
0 ≤ VCM ≤ 3.2		 TJ = 25°C 100 130 dB
The temperature extremes 90
PSRR Power Supply Rejection Ratio TJ = 25°C 95 120 dB
The temperature extremes 90
AVOL Open Loop Voltage Gain RL = 10 kΩ TJ = 25°C 105 130 dB
The temperature extremes 100
RL = 2 kΩ TJ = 25°C 95 132
The temperature extremes 90
VO Output Swing
(LMP2011 only)		 RL = 10 kΩ to 2.5 V,
VIN(diff) = ±0.5 V 		TJ = 25°C 4.96 4.978 V
The temperature extremes 4.95
TJ = 25°C 0.040 0.070
The temperature extremes 0.085
RL = 2 kΩ to 2.5 V,
VIN(diff) = ±0.5 V 		TJ = 25°C 4.895 4.919 V
The temperature extremes 4.875
TJ = 25°C 0.091 0.115
The temperature extremes 0.140
Output Swing
(LMP2012 only)		 RL = 10 kΩ to 2.5 V,
VIN(diff) = ±0.5 V 		TJ = 25°C 4.92 4.978 V
The temperature extremes 4.91
TJ = 25°C 0.040 0.080
The temperature extremes 0.095
RL = 2 kΩ to 2.5 V,
VIN(diff) = ±0.5 V 		TJ = 25°C 4.875 4.919 V
The temperature extremes 4.855
TJ = 25°C 0.0.91 0.125
The temperature extremes 0.150
IO Output Current Sourcing, VO = 0 V,
VIN(diff) = ±0.5 V		 TJ = 25°C 8 15 mA
The temperature extremes 6
Sinking, VO = 5 V,
VIN(diff) = ±0.5 V		 TJ = 25°C 8 17
The temperature extremes 6
IS Supply Current per Channel TJ = 25°C 0.930 1.20 mA
The temperature extremes 1.50
(1) Typical values represent the most likely parametric norm.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.

6.9 5-V AC Electrical Characteristics

TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = 2.5 V, VO = 2.5 V, and RL > 1MΩ.
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX(2) UNIT
GBW Gain-Bandwidth Product 3 MHz
SR Slew Rate 4 V/μs
θ m Phase Margin 60 deg
Gm Gain Margin −15 dB
en Input-Referred Voltage Noise 35 nV/√Hz
enp-p Input-Referred Voltage Noise RS = 100 Ω, DC to 10 Hz 850 nVpp
trec Input Overload Recovery Time 50 ms
(1) Typical values represent the most likely parametric norm.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.

6.10 Typical Characteristics

TA=25C, VS= 5 V unless otherwise specified.
LMP2011 LMP2012 20071555.png Figure 1. Supply Current vs Supply Voltage
LMP2011 LMP2012 20071557.gif Figure 3. Offset Voltage vs Common Mode
LMP2011 LMP2012 20071504.gif Figure 5. Voltage Noise vs Frequency
LMP2011 LMP2012 20071507.gif Figure 7. PSRR vs Frequency
LMP2011 LMP2012 20071559.png Figure 9. Output Sourcing at 2.7 V
LMP2011 LMP2012 20071561.png Figure 11. Output Sinking at 2.7 V
LMP2011 LMP2012 20071563.png Figure 13. Maximum Output Swing vs Supply Voltage
LMP2011 LMP2012 20071565.png Figure 15. Minimum Output Swing vs Supply Voltage
LMP2011 LMP2012 20071505.gif Figure 17. CMRR vs Frequency
LMP2011 LMP2012 20071509.gif Figure 19. Open Loop Gain and Phase vs RL at 2.7 V
LMP2011 LMP2012 20071511.gif Figure 21. Open Loop Gain and Phase vs CL at 2.7 V
LMP2011 LMP2012 20071536.gif Figure 23. Open Loop Gain and Phase vs Temperature
at 2.7 V
LMP2011 LMP2012 20071514.gif Figure 25. THD+N vs AMPL
LMP2011 LMP2012 20071515.gif Figure 27. 0.1 Hz − 10 Hz Noise vs Time
LMP2011 LMP2012 20071556.png Figure 2. Offset Voltage vs Supply Voltage
LMP2011 LMP2012 20071558.png Figure 4. Offset Voltage vs Common Mode
LMP2011 LMP2012 20071503.gif Figure 6. Input Bias Current vs Common Mode
LMP2011 LMP2012 20071506.gif Figure 8. PSRR vs Frequency
LMP2011 LMP2012 20071560.png Figure 10. Output Sourcing at 5 V
LMP2011 LMP2012 20071562.png Figure 12. Output Sinking at 5 V
LMP2011 LMP2012 20071564.png Figure 14. Maximum Output Swing vs Supply Voltage
LMP2011 LMP2012 20071566.png Figure 16. Minimum Output Swing vs Supply Voltage
LMP2011 LMP2012 20071508.gif Figure 18. Open Loop Gain and Phase vs Supply Voltage
LMP2011 LMP2012 20071510.gif Figure 20. Open Loop Gain and Phase vs RL at 5 V
LMP2011 LMP2012 20071512.gif Figure 22. Open Loop Gain and Phase vs CL at 5 V
LMP2011 LMP2012 20071537.gif Figure 24. Open Loop Gain and Phase vs Temperature
at 5 V
LMP2011 LMP2012 20071513.gif Figure 26. THD+N vs Frequency

 
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