The LMP7300 is a combination comparator and reference with ideal specifications for precision threshold detecting. The precision 2.048-V reference comes with a 0.25% maximum error. The comparator features micropower (35 µW), low offset voltage (0.75-mV maximum), and independent adjustable positive and negative hysteresis.
Hysteresis control for the comparator is accomplished through two external pins. The HYSTP pin sets the positive hysteresis, and the HYSTN pin sets the negative hysteresis. The comparator design isolates the VIN source impedance and the programmable hysteresis components. This isolation prevents any undesirable interaction allowing the IC to maintain a precise threshold voltage during level detection.
The combination of low offset voltage, external hysteresis control, and precision voltage reference provides an easy-to-use micropower precision threshold detector.
The LMP7300 open collector output is ideal for mixed-voltage system designs. The output voltage upper rail is unconstrained by VCC and can be pulled above VCC to a maximum of 12 V. The LMP7300 is a member of the LMP precision amplifier family.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMP7300 | VSSOP (8) | 3.00 mm × 3.00 mm |
SOIC (8) | 3.91 mm × 4.90 mm |
Changes from F Revision (March 2013) to G Revision
Changes from E Revision (March 2013) to F Revision
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
+IN | 1 | I | Noninverting Comparator Input. The +IN has a common-mode voltage range from 1 V above the negative rail to, and including, the positive rail. Internal ESD diodes, connected from the +IN pin to the rails, protect the input stage from overvoltage. If the input voltage exceeds the rails, the diodes turn on and clamp the input to a safe level. |
-IN | 2 | I | Inverting Comparator Input. The −IN has a common-mode voltage range from 1 V above the negative rail to, and including, the positive rail. Internal ESD diodes, connected from the −IN pin to the rails, protects the input stage from overvoltage. If the input voltage exceeds the rails, the diodes turn on and clamp the input to a safe level. |
GND | 3 | G | Ground. This pin may be connected to a negative DC voltage source for applications requiring a dual supply. If connected to a negative supply, decouple this pin with 0.1-µF ceramic capacitor to ground. The internal reference output voltage is referenced to this pin. GND is the die substrate connection. |
OUT | 4 | O | Comparator Output. The output is an open-collector. It can drive voltage loads by using a pullup resistor, or it can drive current loads by sinking a maximum output current. This pin may be taken to a maximum of +12 V with respect to the ground pin, irrespective of supply voltage. |
HYSTN | 5 | I | Negative Hysteresis pin. This pin sets the lower trip voltage VIL. The common mode range is from 1V above the negative rail to VCC. The input signal must fall below VIL for the comparator to switch from high to low state. |
HYSTP | 6 | I | Positive Hysteresis pin. This pin sets the upper trip voltage VIH. The common mode range is from 1V above the negative rail to VCC. The input signal must rise above VIH for the comparator to switch from low to high state. |
REF | 7 | O | Reference Voltage Output pin. This is the output pin of a 2.048-V band gap precision reference. |
V+ | 8 | P | Positive Supply Terminal. The supply voltage range is 2.7 V to 12 V. Decouple this pin with 0.1-μF ceramic capacitor to ground. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN differential | ±VS | V | ||
Supply voltage (VS = V+ – V−) | 13.6 | V | ||
Voltage at input/output pins | V+ + 0.3 | V− − 0.3 | V | |
Soldering information | Infrared or convection (20 s) | 235 | °C | |
Wave soldering lead temperature (10 s) | 260 | °C | ||
Junction temperature, TJ(2) | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±250 | |||
Machine model | ±200 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Temperature(2) | –40 | 125 | °C | ||
Supply Voltage (VS = V+ – V−) | 2.7 | 12 | V |
THERMAL METRIC(1) | LMP7300 | UNIT | ||
---|---|---|---|---|
DGK (VSSOP) | D (SOIC) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance(2) | 175.5 | 121.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 66.1 | 67.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 95.6 | 61.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 10 | 18.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 94.2 | 61 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IS | Supply Current | RPULLUP = Open | TA = 25°C | 9 | 12 | μA | |
TJ = TA | 17 | ||||||
COMPARATOR | |||||||
VOS | Input Offset Voltage | VCM = V+/2 SOIC | TA = 25°C | ±0.07 | ±0.75 | mV | |
TJ = TA | ±2 | ||||||
VCM = V+/2 VSSOP | TA = 25°C | ±0.07 | ±1 | mV | |||
TJ = TA | ±2.2 | ||||||
TCVOS | Input Offset Average Drift | See(6) | 1.8 | μV/°C | |||
IB | Input Bias Current(5) | |VID| < 2.5 V | TA = 25°C | 1.2 | 3 | nA | |
TJ = TA | 4 | ||||||
IOS | Input Offset Current | 0.15 | 0.5 | nA | |||
CMRR | Common Mode Rejection Ratio | 1 V < VCM < 2.7 V | 80 | 100 | dB | ||
PSRR | Power Supply Rejection Ratio | V+ = 2.7 V to 12 V | 80 | 100 | dB | ||
VOL | Output Low Voltage | ILOAD = 10 mA | TA = 25°C | 0.25 | 0.4 | V | |
TJ = TA | 0.5 | ||||||
ILEAK | Output Leakage Current | Comparator Output in High State | 1 | pA | |||
HCLIN | Hysteresis Control Voltage Linearity | 0 < Ref-HYSTP,N < 25 mV | 1 | mV/V | |||
25 mV < Ref-HYSTP,N < 100 mV | 0.950 | ||||||
IHYS | Hysteresis Leakage Current | TA = 25°C | 1.2 | 3 | nA | ||
TJ = TA | 4 | ||||||
TPD | Propagation Delay (High to Low) |
Overdrive = 10 mV, CL = 10 pF | 12 | 17 | μs | ||
Overdrive = 100 mV, CL = 10 pF | 4.5 | 7.6 | |||||
REFERENCE | |||||||
VO | Reference Voltage | SOIC | 2.043 | 2.048 | 2.053 | V | |
VSSOP | 2.043 | 2.048 | 2.056 | V | |||
Line Regulation | VCC = 2.7 V to 12 V | 14 | 80 | μV/V | |||
Load Regulation | IOUT = 0 to 1 mA | 0.2 | 0.5 | mV/mA | |||
TCVREF/°C | Temperature Coefficient | −40°C to 125°C | 55 | ppm/°C | |||
VN | Output Noise Voltage | 0.1 Hz to 10 Hz | 80 | μVPP | |||
10 Hz to 10 kHz | 100 | μVRMS |
PARAMETER | TEST CONDITIONS | MIN(4) | TYP(3) | MAX(4) | UNIT | ||
---|---|---|---|---|---|---|---|
IS | Supply Current | RPULLUP = Open | TA = 25°C | 10 | 13 | μA | |
TJ = TA | 18 | ||||||
COMPARATOR | |||||||
VOS | Input Offset Voltage | VCM = V+/2 SOIC | TA = 25°C | ±0.07 | ±0.75 | mV | |
TJ = TA | ±2 | ||||||
VCM = V+/2 VSSOP | TA = 25°C | ±0.07 | ±1 | mV | |||
TJ = TA | ±2.2 | ||||||
TCVOS | Input Offset Average Drift | See(6) | 1.8 | μV/°C | |||
IB | Input Bias Current(5) | |VID| < 2.5 V | TA = 25°C | 1.2 | 3 | nA | |
TJ = TA | 4 | ||||||
IOS | Input Offset Current | 0.15 | 0.5 | nA | |||
CMRR | Common Mode Rejection Ratio | 1 ≤ VCM ≤ 5 V | 80 | 100 | dB | ||
PSRR | Power Supply Rejection Ratio | V+ = 2.7 V to 12 V | 80 | 100 | dB | ||
VOL | Output Voltage Low | ILOAD = 10 mA | 0.25 | 0.4 | V | ||
ILEAK | Output Leakage Current | Comparator Output in High State | 1 | pA | |||
HCLIN | Hysteresis Control Voltage Linearity | 0 < Ref-VHYSTP,N < 25 mV | 1 | mV/V | |||
25 mV < Ref-VHYSTP,N < 100 mV | 0.950 | ||||||
IHYS | Hysteresis Leakage Current | TA = 25°C | 1.2 | 3 | nA | ||
TJ = TA | 4 | ||||||
TPD | Propagation Delay (High to Low) |
Overdrive = 10 mV, CL = 10 pF | 12 | 15 | μs | ||
Overdrive = 100 mV, CL = 10 pF | 4 | 7 | |||||
REFERENCE | |||||||
VO | Reference Voltage | SOIC | 2.043 | 2.048 | 2.053 | V | |
VSSOP | 2.043 | 2.048 | 2.056 | V | |||
Line Regulation | VCC = 2.7 V to 12 V | 14 | 80 | μV/V | |||
Load Regulation | IOUT = 0 to 1 mA | 0.2 | 0.5 | mV/mA | |||
TCVREF/°C | Temperature Coefficient | −40°C to 125°C | 55 | ppm/°C | |||
VN | Output Noise Voltage | 0.1 Hz to 10 Hz | 80 | μVPP | |||
10 Hz to 10 kHz | 100 | μVRMS |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IS | Supply Current | RPULLUP = Open | TA = 25°C | 11 | 14 | µA | |
TJ = TA | 20 | ||||||
COMPARATOR | |||||||
VOS | Input Offset Voltage | VCM = V+/2 SOIC | TA = 25°C | ±0.08 | ±0.75 | mV | |
TJ = TA | ±2 | ||||||
VCM = V+/2 VSSOP | TA = 25°C | ±0.08 | ±1 | mV | |||
TJ = TA | ±2.2 | ||||||
TCVOS | Input Offset Average Drift | See(6) | 1.8 | μV/°C | |||
IB | Input Bias Current(5) | |VID| > 2.5 V | TA = 25°C | 1.2 | 3 | nA | |
TJ = TA | 4 | ||||||
IOS | Input Offset Current | 0.15 | 0.5 | nA | |||
CMRR | Common Mode Rejection Ratio | 1 V ≤ VCM ≤ 12 V | 80 | 100 | dB | ||
PSRR | Power Supply Rejection Ratio | V+ = 2.7 V to 12 V | 80 | 100 | dB | ||
VOL | Output Voltage Low | ILOAD = 10 mA | 0.25 | 0.4 | V | ||
ILEAK | Output Leakage Current | Comparator Output in High State | 1 | pA | |||
HCLIN | Hysteresis Control Voltage Linearity | 0 < Ref-V+HYSTP, N < 25 mV | 1 | mV/V | |||
25 mV < Ref-V+HYSTP, N < 100 mV | 0.95 | ||||||
IHYS | Hysteresis Leakage Current | TA = 25°C | 1.2 | 3 | nA | ||
TJ = TA | 4 | ||||||
TPD | Propagation Delay (High to Low) |
Overdrive = 10 mV, CL = 10 pF | 11 | 15 | μs | ||
Overdrive = 100 mV, CL = 10 pF | 3.5 | 6.8 | |||||
REFERENCE | |||||||
VO | Reference Voltage | TJ = 25°C SOIC | 2.043 | 2.048 | 2.053 | V | |
TJ = 25°C VSSOP | 2.043 | 2.048 | 2.056 | V | |||
Line Regulation | VCC = 2.7 V to 12 V | 14 | 80 | μV/V | |||
Load Regulation | IOUT = 0 to 1 mA | 0.2 | 0.5 | mV/mA | |||
TCVREF/°C | Temperature Coefficient | −40°C to 125°C | 55 | ppm/°C | |||
VN | Output Noise Voltage | 0.1 Hz to 10 Hz | 80 | μVPP | |||
10 Hz to 10 kHz | 100 | μVRMS |