The LMP7721 is the industry’s lowest specified input bias current precision amplifier. The ultra-low input bias current is 3 fA, with a specified limit of ±20 fA at 25°C and ±900 fA at 85°C. This is achieved with the latest patent-pending technology of input bias current cancellation amplifier circuitry. This technology also maintains the ultra-low input bias current over the entire input common-mode voltage range of the amplifier.
Other outstanding features, such as low voltage noise (6.5 nV/√Hz), low DC-offset voltage (±150 µV maximum at 25°C) and low-offset voltage temperature coefficient (−1.5 µV/°C), improve system sensitivity and accuracy in high-precision applications. With a supply voltage range of 1.8 V to 5.5 V, the LMP7721 is the ideal choice for battery-operated, portable applications. The LMP7721 is part of the LMP™ precision amplifier family.
As part of Texas Instruments' PowerWise™ products, the LMP7721 provides the remarkably wide-gain bandwidth product (GBW) of 17 MHz while consuming only 1.3 mA of current. This wide GBW along with the high open-loop gain of 120 dB enables accurate signal conditioning. With these specifications, the LMP7721 has the performance to excel in a wide variety of applications such as electrochemical cell amplifiers and sensor interface circuits.
The LMP7721 is offered in an 8-pin SOIC package with a special pinout that isolates the amplifier’s input from the power supply and output pins. With proper board layout techniques, the unique pinout of the LMP7721 will prevent PCB leakage current from reaching the input pins. Thus system error will be further reduced.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMP7721 | SOIC (8) | 4.90 mm × 3.90 mm |
Changes from D Revision (March 2013) to E Revision
Changes from C Revision (March 2013) to D Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN+ | 1 | I | Non-Inverting Input |
N/C | 2 | - | No Internal Connection (1) |
V- | 3 | P | Negative Power Supply |
VOUT | 4 | O | Output |
N/C | 5 | - | No Internal Connection |
V+ | 6 | P | Positive Power Supply |
N/C | 7 | - | No Internal Connection (1) |
IN- | 8 | I | Inverting Input |
MIN | MAX | UNIT | |
---|---|---|---|
VIN Differential | –0.3 | 0.3 | V |
Supply Voltage (VS = V+ – V−) (3) | –0.3 | 6.0 | V |
Voltage on Input/Output Pins | V+ + 0.3 | V− − 0.3 | V |
Junction Temperature (2) | 150 | °C | |
Soldering Information | |||
Infrared or Convection (20 sec) | 235 | °C | |
Wave Soldering Lead Temp. (10 sec) | 260 | °C | |
Storage temperature, Tstg | −65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±200 |
MIN | MAX | UNIT | |
---|---|---|---|
Temperature Range(2) | –40 | 125 | °C |
Supply Voltage (VS = V+ – V−): | |||
0°C ≤ TA ≤ 125°C | 1.8 | 5.5 | V |
−40°C ≤ TA ≤ 125°C | 2.0 | 5.5 | V |
THERMAL METRIC(1) | LMP7721 | UNIT | |
---|---|---|---|
D | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 190 | °C/W |
PARAMETER | TEST CONDITIONS | MIN(2) | TYP(1) | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
VOS | Input Offset Voltage | –180 | ±50 | 180 | μV | ||
–40°C ≤ TJ ≤ 125°C | –480 | 480 | |||||
TC VOS | Input Offset Voltage Drift (3) |
–1.5 | –4 | μV/°C | |||
IBIAS | Input Bias Current | VCM = 1 V(4)(5) | 25°C | –20 | ±3 | 20 | fA |
−40°C to 85°C | –900 | 900 | |||||
−40°C to 125°C | –5 | 5 | pA | ||||
IOS | Input Offset Current | VCM = 1 V(5) | ±6 | ±40 | fA | ||
CMRR | Common-Mode Rejection Ratio | 0 V ≤ VCM ≤ 1.4 V | 83 | 100 | dB | ||
0 V ≤ VCM ≤ 1.4 V, –40°C ≤ TJ ≤ 125°C | 80 | ||||||
PSRR | Power Supply Rejection Ratio | 1.8 V ≤ V+ ≤ 5.5 V, V− = 0 V, VCM = 0 | 84 | 92 | dB | ||
1.8 V ≤ V+ ≤ 5.5 V, V− = 0 V, VCM = 0, –40°C ≤ TJ ≤ 125°C | 80 | ||||||
CMVR | Input Common-Mode Voltage Range | CMRR ≥ 80 dB | −0.3 | 1.5 | V | ||
CMRR ≥ 78 dB, –40°C ≤ TJ ≤ 125°C | –0.3 | 1.5 | |||||
AVOL | Large Signal Voltage Gain | VO = 0.15 V to 2.2 V, RL = 2 kΩ to V+/2 | 88 | 107 | dB | ||
VO = 0.15 V to 2.2 V, RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 82 | ||||||
VO = 0.15 V to 2.2 V, RL = 10 kΩ to V+/2 | 92 | 120 | |||||
VO = 0.15 V to 2.2 V, RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 88 | ||||||
VO | Output Swing High | RL = 2 kΩ to V+/2 | 70 | 25 | mV from V+ |
||
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 77 | ||||||
RL = 10 kΩ to V+/2 | 60 | 20 | |||||
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 66 | ||||||
Output Swing Low | RL = 2 kΩ to V+/2 | 30 | 70 | mV | |||
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 73 | ||||||
RL = 10 kΩ to V+/2 | 15 | 60 | |||||
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 62 | ||||||
IO | Output Short Circuit Current | Sourcing to V−, VIN = 200 mV (6) | 36 | 46 | mA | ||
Sourcing to V−, VIN = 200 mV (6), –40°C ≤ TJ ≤ 125°C | 30 | ||||||
Sinking to V+, VIN = −200 mV (6) | 7.5 | 15 | |||||
Sinking to V+, VIN = −200 mV (6), –40°C ≤ TJ ≤ 125°C | 5.0 | ||||||
IS | Supply Current | 1.1 | 1.5 | mA | |||
–40°C ≤ TJ ≤ 125°C | 1.75 | ||||||
SR | Slew Rate | AV = +1, Rising (10% to 90%) | 9.3 | V/μs | |||
AV = +1, Falling (90% to 10%) | 10.8 | ||||||
GBW | Gain Bandwidth Product | 15 | MHz | ||||
en | Input-Referred Voltage Noise | f = 400 Hz | 8 | nV/![]() |
|||
f = 1 kHz | 7 | ||||||
In | Input-Referred Current Noise | f = 1 kHz | 0.01 | pA/![]() |
|||
THD+N | Total Harmonic Distortion + Noise | f = 1 kHz, AV = 2, RL = 100 kΩ VO = 0.9 VPP |
0.003% | ||||
f = 1 kHz, AV = 2, RL = 600 Ω VO = 0.9 VPP |
0.003% |
PARAMETER | TEST CONDITIONS | MIN(2) | TYP(1) | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
VOS | Input Offset Voltage | –150 | ±26 | 150 | μV | ||
–40°C ≤ TJ ≤ 125°C | 450 | 450 | |||||
TC VOS | Input Offset Average Drift (3) |
–1.5 | –4 | μV/°C | |||
IBIAS | Input Bias Current | VCM = 1 V(4)(5) | 25°C | –20 | ±3 | 20 | fA |
−40°C to 85°C | –900 | 900 | |||||
−40°C to 125°C | –5 | 5 | pA | ||||
IOS | Input Offset Current | (5) | ±6 | ±40 | fA | ||
CMRR | Common-Mode Rejection Ratio | 0 V ≤ VCM ≤ 3.7 V | 84 | 100 | dB | ||
0 V ≤ VCM ≤ 3.7 V, –40°C ≤ TJ ≤ 125°C | 82 | ||||||
PSRR | Power Supply Rejection Ratio | 1.8 V ≤ V+ ≤ 5.5 V, V− = 0 V, VCM = 0 | 84 | 96 | dB | ||
1.8 V ≤ V+ ≤ 5.5 V, V− = 0 V, VCM = 0, –40°C ≤ TJ ≤ 125°C | 80 | ||||||
CMVR | Input Common-Mode Voltage Range | CMRR ≥ 80 dB | −0.3 | 4 | V | ||
CMRR ≥ 78 dB, –40°C ≤ TJ ≤ 125°C | –0.3 | 4 | |||||
AVOL | Large Signal Voltage Gain | VO = 0.3 V to 4.7 V, RL = 2 kΩ to V+/2 | 88 | 111 | dB | ||
VO = 0.3 V to 4.7 V, RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 82 | ||||||
VO = 0.3 V to 4.7 V, RL = 10 kΩ to V+/2 | 92 | 120 | |||||
VO = 0.3 V to 4.7 V, RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 88 | ||||||
VO | Output Swing High | RL = 2 kΩ to V+/2 | 70 | 30 | mV from V+ |
||
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 77 | ||||||
RL = 10 kΩ to V+/2 | 60 | 20 | |||||
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 66 | ||||||
Output Swing Low | RL = 2 kΩ to V+/2 | 31 | 70 | mV | |||
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 73 | ||||||
RL = 10 kΩ to V+/2 | 20 | 60 | |||||
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C | 62 | ||||||
IO | Output Short Circuit Current | Sourcing to V−, VIN = 200 mV (6) | 46 | 60 | mA | ||
Sourcing to V−, VIN = 200 mV (6), –40°C ≤ TJ ≤ 125°C | 38 | ||||||
Sinking to V+, VIN = −200 mV (6) | 10.5 | 22 | |||||
Sinking to V+, VIN = −200 mV (6), –40°C ≤ TJ ≤ 125°C | 6.5 | ||||||
IS | Supply Current | 1.3 | 1.7 | mA | |||
–40°C ≤ TJ ≤ 125°C | 1.95 | ||||||
SR | Slew Rate | AV = +1, Rising (10% to 90%) | 10.43 | V/μs | |||
AV = +1, Falling (90% to 10%) | 12.76 | ||||||
GBW | Gain Bandwidth Product | 17 | MHz | ||||
en | Input-Referred Voltage Noise | f = 400 Hz | 7.5 | nV/![]() |
|||
f = 1 kHz | 6.5 | ||||||
In | Input-Referred Current Noise | f = 1 kHz | 0.01 | pA/![]() |
|||
THD+N | Total Harmonic Distortion + Noise | f = 1 kHz, AV = 2, RL = 100 kΩ VO = 4 VPP |
0.0007% | ||||
f = 1 kHz, AV = 2, RL = 600Ω VO = 4 VPP |
0.0007% |
The LMP7721 combines a patented input bias current cancelling circuitry along with an optimized pinout to provide and ultra-low maximum specified bias current of ±20 fA.
The LMP7721 has the industry’s lowest specified input bias current. The ultra-low input bias current is typically 3 fA, with a specified limit of ±20 fA at 25°C, ±900 fA at 85°C and ±5 pA at 125°C when VCM = 1 V with a 5-V or a 2.5-V power supply.
The LMP7721 is a high-performance amplifier that provides a 17-MHz unity gain bandwidth while drawing only 1.3 mA of current. This makes the LMP7721 ideal for wideband amplification in portable applications.
The LMP7721 has a low input-referred voltage noise density (6.5 nV at 1 kHz with 5-V supply). Its MOS input stage ensures a very low input-referred current noise density (0.01 pA/
).
The low input-referred noise and the ultra-low input bias current make the LMP7721 stand out in maintaining signal fidelity. This quality makes the LMP7721 a suitable candidate for sensor-based applications.
The LMP7721 has performance specified at 2.5-V and 5-V power supplies. The LMP7721 is ensured to be functional at all supply voltages between 2 V to 5.5 V, for ambient temperatures ranging from −40°C to 125°C. This means that the LMP7721 has a long operational span over the battery's lifetime. The LMP7721 is also specified to be functional at 1.8-V supply voltage, for ambient temperatures ranging from 0°C to 125°C. This makes the LMP7721 ideal for use in low-voltage commercial applications.
Rail-to-rail output swing provides the maximum possible output dynamic range. This is particularly important when operating at low-supply voltages. An innovative positive feedback scheme is created to boost the LMP7721’s output current drive capability. This allows the LMP7721 to source 30 mA to 40 mA of current at 1.8-V power supply.
The LMP7721’s input common-mode range includes the negative supply rail which makes direct sensing at ground possible in single-supply operation.
The LMP7721 has been designed with the IN+ and IN−, V+ and V− pins on opposite sides of the package. There are isolation pins between IN+ and V−, IN− and V+. This unique pinout makes it easy to guard the LMP7721’s input. This pinout design reduces the input bias current’s dependence on common mode or supply bias.
The SOIC package features low leakage and it has large pin spacing. This lowers the probability of dust particles settling down between two pins thus reducing the resistance between the pins which can be a problem.
The two No Connect (N/C) isolation pins are not internally connected and may be tied to the guard trace to provide down-into-the-package level guarding of the inputs.
The LMP7721 input stage is protected from seeing excessive differential input voltage by a pair of back-to-back diodes attached between the inputs. This limits the differential voltage and hence prevents phase inversion as well as any performance drift. These diodes can conduct current when the input signal has a really fast edge, and, if necessary, should be isolated (using a resistor or a current follower) in such cases. Under normal feedback operation, the average differential voltage is less than 1 mV and these diodes do not affect the normal operation of the device. This clamp also limits the use as a comparator, which is not a recommended function for operational amplifiers.
The high-input resistance of the LMP7721 allows the use of large feedback and source resistor values without losing gain accuracy due to loading. However, the circuit will be especially sensitive to its layout when these large-value resistors are used.
Every amplifier has some capacitance between each input and AC ground, and also some differential capacitance between the inputs. When the feedback network around an amplifier is resistive, this input capacitance (along with any additional capacitance due to circuit board traces, the socket, etc.) and the feedback resistors create a pole in the feedback path. This pole can cause gain "peaking" or outright oscillations.
In the General Operational Amplifier circuit, Figure 45 the frequency of this pole is:
where:
The typical input capacitance of the LMP7721 is about 11pF. This formula, as well as all formulas derived below, apply to inverting and non-inverting op amp configurations.
When the feedback resistors are smaller than a few kΩ, the frequency of the feedback pole will be quite high, since CS is generally less than 15 pF. If the frequency of the feedback pole is much higher than the “ideal” closed-loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole will have a negligible effect on stability, as it will add only a small amount of phase shift.
However, if the feedback pole is less than approximately 6 to 10 times the “ideal” −3 dB frequency, a feedback capacitor, CF, should be connected between the output and the inverting input of the op amp. This condition can also be stated in terms of the amplifier’s low-frequency noise gain: To maintain stability a feedback capacitor will probably be needed if
where
is the amplifier’s low-frequency noise gain and GBW is the amplifier’s gain bandwidth product. An amplifier’s low-frequency noise gain is represented by the formula
regardless of whether the amplifier is being used in inverting or noninverting mode. Note that a feedback capacitor is more likely to be needed when the noise gain is low and/or the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor will probably be needed), and the noise gain is large enough that:
the following value of feedback capacitor is recommended:
If
the feedback capacitor should be:
Note that these capacitor values are usually significant smaller than those given by the older, more conservative formula:
NOTE
CS consists of the amplifier’s input capacitance plus any stray capacitance from the circuit board. CF compensates for the pole caused by CS and the feedback resistors.
Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease the noise or bandwidth, or simply because the particular circuit implementation needs more feedback capacitance to be sufficiently stable. For example, a printed circuit board’s stray capacitance may be larger or smaller than the breadboard’s, so the actual optimum value for CF may be different from the one estimated using the breadboard. In most cases, the values of CF should be checked on the actual circuit, starting with the computed value.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LMP7721 is specified for operation from 1.8 V to 5.5 V. Many of the specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics section.
In order to take full advantage of the LMP7721’s ultra-low input bias current, a "Guard" trace is recommended when designing sub-nanoamp systems.
A "Guard" is a driven trace or shield that physically surrounds the input trace and feedback circuitry that is held at a potential equal to the average input signal potential. Since the input circuitry and the guard are kept at the same potential, the leakage current between the two nodes is practically zero. The guard is a low-impedance node, so any external leakages will "leak" into the guard and not into the protected input. One benefit of using a guard is it cancels the effect of the added stray and cable capacitance at low frequencies (but cannot cancel the sensor or amplifier input capacitance).
The guard potential may be taken from the inverting input (summing node) in noninverting and buffer applications. An example of this is shown in Figure 47 If the guarding needs to extend beyond the immediate local area around the IC, then a buffer should be used to drive the guard to prevent adding additional capacitance to the inverting node.
The guard potential may be taken from the noninverting input or reference voltage in inverting or transimpedance applications. An example of this is shown in Figure 48
The gain of the buffer should be slightly less than one to prevent oscillations and should be current limited to protect against short circuits. The buffer amplifier should also be capable of driving large capacitive loads. To satisfy these two requirements, a small series output resistor is usually placed on the buffer output in the range of 100 Ω to 1 kΩ.
For optimum results, the guard should completely enclose the input circuitry within a conductive "cocoon", including above and below the circuitry. A cover or shield connected to the guard should protect the circuitry above (or below) the PC board. Do not forget about thru-hole devices (like leaded photodiodes or connectors) that may expose high-impedance nodes to the opposite side of the board.
The guard trace should not be relied upon as the only method of shielding. A ground plane or shield should surround and protect the guard from large external leakages and noise, as the guard trace has the potential to couple noise back into the input. For more information on guarding, please see the articles referenced in Related Documentation.
A triaxial cable or connector is similar to a coaxial cable or connector and is often referred to as “triax”. The triaxial cable extends the guard protection through the length of the cable by adding a second internal guard "shield" around the center conductor in addition to the outer ground shield. Figure 49 shows the structure of the triax connector.
Proper cleaning of the board is very critical to providing the expected sub-picoamp performance. Properly cleaning the board and components takes a few extra steps over conventional board cleaning methods. Leftover flux residue, moisture and cleaning solvent residues will severely degrade the low-current performance.
If using "water soluble" or "no clean" flux, a second cleaning step is needed. These fluxes still leave a film behind that can attract contaminates and dust. The board should be washed with fresh isopropyl alcohol or methanol and baked to make sure all remaining traces of moisture are removed from the board. Areas between the component leads should be scrubbed and areas under surface mount devices thoroughly flushed. The board should be re-cleaned after any rework to components within the guarded areas. Boards should be handled by the edges and stored in sealed containers with desiccant.
The following application examples highlight only a few of the circuits where the LMP7721 can be used.
A CMOS input stage with ultra-low input bias current, negligible input current noise, and low input voltage noise allows the LMP7721 to provide high fidelity amplification. In addition, the LMP7721 has a 17 MHz gain bandwidth product, which enables high gain at wide bandwidth. A rail-to-rail output swing at 5.5-V power supply allows detection and amplification of a wide range of input currents. These properties make the LMP7721 ideal for transimpedance amplification.
The output of a pH electrode is typically 59.16 mV per pH unit at 25°C, for an output range of 414 mV to −414 mV as the pH changes from 0 to 14 at 25°C.
The output impedance of a pH electrode is extremely high, ranging from 10 MΩ to 1000 MΩ. The ultra low input bias current of the LMP7721 allows the voltage error produced by the input bias current and electrode resistance to be minimal. For example, the output impedance of the pH electrode used is 10 MΩ, if an op amp with 3 nA of Ibias is used, the error caused due to this amplifier’s input bias current and the source resistance of the pH electrode is 30 mV! This error can be greatly reduced to 30 nV by using the LMP7721.
The output voltage of the pH electrode will range from 54.2 mV/pH at 0°C, to 74.04 mV/pH at 100°C. The maximum input voltage will then be ±74.04 mV * 7 = ±518.3 mV. Allowing for output swing and offset headroom, the maximum output swing should be limited to ±2.4V. The amplifier gain would then be 2.4 V / 0.5183 V = 4.6 V/V.
With RF = 3.57 kΩ and RG = 1 kΩ, the gain would be 4.57 V/V.
The output voltage from the pH electrode is fed to the signal conductor of the triax and then sent to the non-inverting input of the LMP7721. In this application, the inverting input is a low impedance node and hence is used to drive the LMP7715 which acts as a guard driver. The output of the guard driver is connected to the guard of the triax through a 100-Ω isolation resistor.
Figure 50 is an example of the LMP7721 used as a pH sensor amplifier.
For high-sensitivity applications, the power supply rails should be as clean as possible.
Noise on the power supply lines can modulate the tiny capacitance (about 0.5 pF) of the ESD structure on each input. While this is not a major concern for most applications, charge-sensitive or high-gain, high-impedance applications can be affected. Common results are power line "hum" or high-frequency switcher "hash" imposed on the signal.
TI recommends using a very low noise linear regulator and add a dedicated filter network to the LMP7721 power supply pins consisting of a series resistor of about 100 Ω, and a bypass capacitor of 100 uF or larger. Series inductors or ferrite beads may be required if high frequency switcher noise is present.