SNAS510S January   2011  – January 2016 LMP90097 , LMP90098 , LMP90099 , LMP90100

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Schematic
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  SPI Timing Requirements
    7. 8.7  CBS Setup and Hold Timing Requirements
    8. 8.8  SCLK and SDI Timing Requirements
    9. 8.9  SDO Timing Requirements
    10. 8.10 SDO and DRDYB Timing Requirements
    11. 8.11 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 True Continuous Background Calibration
      2. 9.3.2 Continuous Background Sensor Diagnostics
      3. 9.3.3 Flexible Input MUX Channels
      4. 9.3.4 Programmable Gain Amplifiers (FGA and PGA)
      5. 9.3.5 Excitation Current Sources (IB1 and IB2) - LMP90100/LMP90098
      6. 9.3.6 Signal Path
        1. 9.3.6.1 Reference Input (VREF)
        2. 9.3.6.2 Flexible Input MUX (VIN)
        3. 9.3.6.3 Selectable Gains (FGA and PGA)
        4. 9.3.6.4 Buffer (BUFF)
        5. 9.3.6.5 Internal/External CLK Selection
        6. 9.3.6.6 Programmable ODRs
        7. 9.3.6.7 Digital Filter
        8. 9.3.6.8 GPIO (D0-D6)
      7. 9.3.7 Calibration
        1. 9.3.7.1 Background Calibration
          1. 9.3.7.1.1 Types of Background Calibration
          2. 9.3.7.1.2 Using Background Calibration
        2. 9.3.7.2 System Calibration
          1. 9.3.7.2.1 System Calibration Offset Coefficient Determination Mode
          2. 9.3.7.2.2 System Calibration Gain Coefficient Determination Mode
          3. 9.3.7.2.3 Post-Calibration Scaling
      8. 9.3.8 Sensor Interface
        1. 9.3.8.1 IB1 and IB2 - Excitation Currents
        2. 9.3.8.2 Burnout Currents
          1. 9.3.8.2.1 Burnout Current Injection
        3. 9.3.8.3 Sensor Diagnostic Flags
          1. 9.3.8.3.1 SHORT_THLD_FLAG
          2. 9.3.8.3.2 RAILS_FLAG
          3. 9.3.8.3.3 POR_AFT_LST_RD:
          4. 9.3.8.3.4 OFLO_FLAGS
          5. 9.3.8.3.5 SAMPLED_CH
      9. 9.3.9 RESET and RESTART
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Management
      2. 9.4.2 Channels Scan Mode
        1. 9.4.2.1 ScanMode0: Single-Channel Continuous Conversion
        2. 9.4.2.2 ScanMode1: Multiple-Channels Single Scan
        3. 9.4.2.3 ScanMode2: Multiple-Channels Continuous Scan
        4. 9.4.2.4 ScanMode3: Multiple-Channels Continuous Scan with Burnout Currents
    5. 9.5 Programming
      1. 9.5.1  General Rules
      2. 9.5.2  Serial Digital Interface
      3. 9.5.3  Register Address (ADDR)
      4. 9.5.4  Register Read/Write Protocol
      5. 9.5.5  Streaming
      6. 9.5.6  CSB - Chip Select Bar
      7. 9.5.7  SPI Reset
      8. 9.5.8  DRDYB - Data Ready Bar
      9. 9.5.9  DRDYB Case1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00
      10. 9.5.10 DRDYB Case2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03
      11. 9.5.11 DRDYB Case3: Routing DRDYB to D6
      12. 9.5.12 Data Only Read Transaction
      13. 9.5.13 Cyclic Redundancy Check (CRC)
      14. 9.5.14 Register Read/Write Examples
        1. 9.5.14.1 Writing To Register Examples
        2. 9.5.14.2 Reading From Register Example
      15. 9.5.15 Streaming Examples
        1. 9.5.15.1 Normal Streaming Example
        2. 9.5.15.2 Controlled Streaming Example
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Quick Start
      2. 10.1.2 ADC_DOUT Calculation
    2. 10.2 Typical Applications
      1. 10.2.1 3-Wire RTD Using 2 Current Sources
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 3-Wire RTD Using 1 Current Source
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Thermocouple with Cold Junction Compensation
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
      4. 10.2.4 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 VA and VIO
    2. 11.2 VREF
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
        1. 13.1.1.1 Specific Definitions
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Device and Documentation Support

13.1 Device Support

13.1.1 Device Nomenclature

13.1.1.1 Specific Definitions

    CMRR

    = 20 LOG(ΔCommon Input / ΔOutput Offset)

    COMMON MODE REJECTION RATIO

    is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed.

    EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) –

    says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. LMP90xxx’s ENOB is a DC ENOB spec, not the dynamic ENOB that is measured using FFT and SINAD. Its equation is as follows:

    Equation 17. LMP90100 LMP90099 LMP90098 LMP90097 30139513.gif
    GAIN ERROR

    is the deviation from the ideal slope of the transfer function.

    INTEGRAL NON-LINEARITY (INL)

    is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point fit method is used. INL for this product is specified over a limited range, per the Electrical Tables.

    NEGATIVE FULL-SCALE ERROR

    is the difference between the differential input voltage at which the output code transitions to negative full scale and (-VREF + 1LSB).

    NEGATIVE GAIN ERROR

    is the difference between the negative full-scale error and the offset error divided by (VREF / Gain).

    NOISE FREE RESOLUTION

    is a method of specifying the number of bits for a converter with noise.

    Equation 18. LMP90100 LMP90099 LMP90098 LMP90097 30139514.gif
    ODR

    Output Data Rate.

    OFFSET ERROR

    is the difference between the differential input voltage at which the output code transitions from code 0000h to 0001h and 1 LSB.

    POSITIVE FULL-SCALE ERROR

    is the difference between the differential input voltage at which the output code transitions to positive full scale and (VREF – 1LSB).

    POSITIVE GAIN ERROR

    is the difference between the positive full-scale error and the offset error divided by (VREF / Gain).

    POWER SUPPLY REJECTION RATIO (PSRR)

    is a measure of how well a change in the analog supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB.

    PSRR

    = 20 LOG (ΔVA / ΔOutput Offset)

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 36. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY
LMP90100 Click here Click here Click here Click here Click here
LMP90099 Click here Click here Click here Click here Click here
LMP90098 Click here Click here Click here Click here Click here
LMP90097 Click here Click here Click here Click here Click here

13.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

13.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.