SNVSBP4C March   2020  – January 2021 LMQ61460-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Characteristics
    7. 8.7 Systems Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  EN/SYNC Uses for Enable and VIN UVLO
      2. 9.3.2  EN/SYNC Pin Uses for Synchronization
      3. 9.3.3  Adjustable Switching Frequency
      4. 9.3.4  Clock Locking
      5. 9.3.5  PGOOD Output Operation
      6. 9.3.6  Internal LDO, VCC UVLO, and BIAS Input
      7. 9.3.7  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      8. 9.3.8  Adjustable SW Node Slew Rate
      9. 9.3.9  Spread Spectrum
      10. 9.3.10 Soft Start and Recovery From Dropout
      11. 9.3.11 Output Voltage Setting
      12. 9.3.12 Overcurrent and Short Circuit Protection
      13. 9.3.13 Thermal Shutdown
      14. 9.3.14 Input Supply Current
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 Auto Mode - Light Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode - Light Load Operation
        4. 9.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 9.4.3.5 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Choosing the Switching Frequency
        2. 10.2.2.2  Setting the Output Voltage
        3. 10.2.2.3  Inductor Selection
        4. 10.2.2.4  Output Capacitor Selection
        5. 10.2.2.5  Input Capacitor Selection
        6. 10.2.2.6  BOOT Capacitor
        7. 10.2.2.7  BOOT Resistor
        8. 10.2.2.8  VCC
        9. 10.2.2.9  BIAS
        10. 10.2.2.10 CFF and RFF Selection
        11. 10.2.2.11 External UVLO
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground and Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.12 Overcurrent and Short Circuit Protection

The device is protected from overcurrent conditions with cycle-by-cycle current limiting on both the high-side and the low-side MOSFETs.

High-side MOSFET overcurrent protection is implemented by the nature of the peak-current mode control. The HS switch current is sensed when the HS is turned on after a short blanking time. Every switching cycle, the HS switch current is compared to either the minimum of a fixed current set point or the output of the voltage regulation loop minus slope compensation. Because the voltage loop has a maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased duty cycle when duty cycle is above 35%. See Figure 9-12.

GUID-62E04386-C3A7-46AA-90A6-780F92507E75-low.gif Figure 9-12 Maximum Current Allowed Through the HS FET - Function of Duty Cycle for LMQ61460-Q1

When the LS switch is turned on, the switch current is also sensed and monitored. Like the high-side device, the low-side device turns off as commanded by the voltage control loop, low-side current limit. If the LS switch current is higher than ILS_Limit at the end of a switching cycle, the switching cycle is extended until the LS current reduces below the limit. The LS switch is turned off once the LS current falls below its limit, and the HS switch is turned on again as long as at least one clock period has passed since the last time the HS device has turned on.

GUID-6E15134B-D605-49F0-B2CD-8E8BB17218FF-low.gifFigure 9-13 Current Limit Waveforms

Since the current waveform assumes values between IL-HS and IL-LS, the maximum output current is very close to the average of these two values. Hysteretic control is used and current does not increase as output voltage approaches zero.

The device employs hiccup overcurrent protection if there is an extreme overload, and the following conditions are met for 128 consecutive switching cycles:

  • Output voltage is below approximately 0.4 times the output voltage set point.
  • Greater than tSS2 has passed since soft start has started; see Section 9.3.10.
  • The part is not operating in dropout, which is defined as having minimum off-time controlled duty cycle.

In hiccup mode, the device shuts itself down and attempts to soft start after tW. Hiccup mode helps reduce the device power dissipation under severe overcurrent conditions and short circuits. See Figure 9-14.

Once the overload is removed, the device recovers as though in soft start; see Figure 9-15.

GUID-3F73F5BC-9A88-489A-8379-7162B53E7E77-low.gifFigure 9-14 Inductor Current Bursts During Hiccup
GUID-B96D4FB9-94DD-46C5-BAAB-0E31FA4FF5ED-low.gifFigure 9-15 Short-Circuit Recovery