SNVSBV1D February 2022 – November 2024 LMQ66410-Q1 , LMQ66420-Q1 , LMQ66430-Q1
PRODUCTION DATA
Synchronized operation of multiple regulators in a single system is often desirable for a well-defined system level performance. The select variants in the device with the MODE/SYNC pin allow the power designer to synchronize the device to a common external clock. The device implements an in-phase locking scheme, where the rising edge of the clock signal, provided to the MODE/SYNC pin of the device, corresponds to the turning on of the high-side device. The external clock synchronization is implemented using a phase locked loop (PLL), eliminating any large glitches. The external clock fed into the device replaces the internal free-running clock, but does not affect any frequency foldback operation. Output voltage continues to be well regulated. The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided. The range of frequencies permitted by the device is given by fSYNC and is provided in the Electrical Characteristics.
The MODE/SYNC input pin in the device can operate in one of three selectable modes: