SNVSBV1D February 2022 – November 2024 LMQ66410-Q1 , LMQ66420-Q1 , LMQ66430-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE (VIN PIN) | ||||||
VINMIN | Input voltage rising threshold for start-up | Before start-up | 3.2 | 3.35 | 3.5 | V |
Input voltage falling threshold | Once operating | 2.45 | 2.7 | 3 | V | |
ISD(VIN) | Shutdown quiescent current at VIN pin | EN = 0V | 0.25 | 1 | µA | |
IBIAS | Non-switching input current at VOUT/FB | Fixed 5.0V Vout, VVOUT/FB = 5.25V | 4.2 | 6.5 | µA | |
IBIAS | Non-switching input current at VOUT/FB | Fixed 3.3Vout, VVOUT/FB = 3.47V | 4.2 | 6.5 | µA | |
IQVIN(nonsw) | Non-switching input current; measured at VIN pin (1) | Fixed 5-V VOUT, VVOUT/FB = 5.25 V | 1.6 | 3 | µA | |
IQVIN(nonsw) | Non-switching input current; measured at VIN pin (1) | Fixed 3.3V VOUT, VVOUT/FB = 3.47V | 1.2 | 2.2 | µA | |
ENABLE (EN PIN) | ||||||
VEN-WAKE | EN wakeup threshold | 0.5 | 0.7 | 1 | V | |
VEN-VOUT | Precision enable rising threshold for VOUT | 1.16 | 1.23 | 1.3 | V | |
VEN-HYST | Enable hysteresis below VEN-VOUT | 0.3 | 0.35 | 0.4 | V | |
ILKG-EN | Enable pin input leakage current | VEN = VIN = 13.5V | 10 | nA | ||
INTERNAL LDO (VCC PIN) | ||||||
VCC | VCC pin output voltage | VFB = 0V, IVCC = 1mA | 3.1 | 3.3 | 3.45 | V |
VOLTAGE FEEDBACK (VOUT/FB PIN) | ||||||
VOUT | Output voltage accuracy for fixed VOUT | 3.3V VOUT, VIN = 3.6V to 36V, FPWM mode | 3.27 | 3.3 | 3.32 | V |
5V VOUT, VIN = 5.5V to 36V, FPWM mode | 4.94 | 5.00 | 5.06 | V | ||
VFB | Internal reference voltage accuracy | VOUT = 1V, VIN = 3.0V to 36V, FPWM mode | 0.99 | 1.00 | 1.01 | V |
IFB(LKG) | FB input current | Adjustable configuration, FB = 1V | 10 | nA | ||
CURRENT LIMITS | ||||||
IPEAKMAX | High-side peak current limit | LMQ66430-Q1 | 3.9 | 4.4 | 5 | A |
IVALMAX | Low-side valley current limit | LMQ66430-Q1 | 2.9 | 3.5 | 4 | A |
IPEAKMIN | Minimum peak current limit | LMQ66430-Q1, Auto mode | 0.55 | 0.69 | 0.86 | A |
INEGMIN | Low-side valley current negative limit | LMQ66430-Q1, FPWM mode | -1.5 | -1.3 | -1 | A |
IPEAKMAX | High-side peak current limit | LMQ66420-Q1 | 2.8 | 3.4 | 3.9 | A |
IVALMAX | Low-side valley current limit | LMQ66420-Q1 | 1.9 | 2.2 | 2.53 | A |
IPEAKMIN | Minimum peak current limit | LMQ66420-Q1, Auto mode | 0.37 | 0.5 | 0.65 | A |
INEGMIN | Negative current limit | LMQ66420-Q1, FPWM mode | -1 | -0.8 | -0.6 | A |
IPEAKMAX | High-side peak current limit | LMQ66410-Q1 | 1.4 | 1.8 | 2.1 | A |
IVALMAX | Low-side valley current limit | LMQ66410-Q1 | 0.9 | 1.1 | 1.4 | A |
IPEAKMIN | Minimum peak current limit | LMQ66410-Q1, Auto mode | 0.17 | 0.27 | 0.35 | A |
INEGMIN | Low-side valley current negative limit | LMQ66410-Q1, FPWM mode | -1 | -0.8 | -0.6 | A |
IZC | Zero-cross current limit | Auto mode | 30 | 80 | 135 | mA |
POWER GOOD (PG PIN) | ||||||
PGOV | PG upper threshold - rising | % of VOUT/FB (Fixed or Adj. output) | 104 | 108 | 111 | % |
PGUV | PG upper threshold - falling | % of VOUT/FB (Fixed or Adj. output) | 89 | 91 | 94.2 | % |
PGHYST | PG recovery hysteresis for OV | % of VOUT/FB target regulation voltage | 2 | 2.4 | 2.8 | % |
PG recovery hysteresis for UV | % of VOUT/FB target regulation voltage | 2 | 3.3 | 4.6 | % | |
VPG-VAL | Minimum VIN for PG function | VEN = 0V, RPG_PU = 10kΩ | 1.5 | V | ||
RPG | PG ON resistance | VEN = 3.3V, 200µA pullup current | 100 | Ω | ||
RPG | PG ON resistance | VEN = 0V, 200µA pullup current | 100 | Ω | ||
tRESET_FILTER | PG deglitch delay at falling edge | 25 | 40 | 75 | µs | |
tPG_ACT | Delay time to PG high signal | 1.35 | 2.5 | 4 | ms | |
SOFT START | ||||||
tSS | Time from first SW pulse to VOUT/FB at 90% of set point | 2 | 3.5 | 4.6 | ms | |
tHICCUP | Time in hiccup before retry soft start | 30 | 50 | 75 | ms | |
OSCILLATOR (SYNC/MODE PIN) | ||||||
tPULSE_H | High duration needed to be recognized as a pulse | 100 | ns | |||
tPULSE_L | Low duration needed to be recognized as a pulse | 100 | ns | |||
tSYNC | High/Low level pulse maximum duration to be recognized as a valid clock signal | 6 | µs | |||
tMODE | Time at one level needed to indicate FPWM or Auto Mode | 12.5 | µs | |||
FSW(400kHz) | Switching Frequency with fixed 400kHz | 340 | 400 | 460 | kHz | |
FSW(2.2MHz) | Switching Frequency with fixed 2.2MHz | 2100 | 2200 | 2300 | kHz | |
fSYNC | Frequency SYNC range | 0.2 | 2.5 | MHz | ||
VMODE_L | SYNC/MODE input voltage low level threshold | 1 | V | |||
VMODE_H | SYNC/MODE input voltage high level threshold | 1.6 | V | |||
SWITCH NODE | ||||||
tON-MIN | Minimum HS switch on-time | FPWM mode IOUT = 1A, 2.2MHz fixed | 65 | 75 | ns | |
tOFF-MIN | Minimum HS switch off-time | 60 | 85 | ns | ||
tON-MAX | Maximum HS switch on-time | HS timeout in dropout | 6 | 9 | 13 | µs |
POWER STAGE | ||||||
VBOOT_UVLO | Voltage on BOOT pin compared to SW which will turnoff high-side switch | 2.1 | V | |||
RDSON-HS | High-side MOSFET on-resistance | Load = 1A | 132 | 260 | mΩ | |
RDSON-LS | Low-side MOSFET on-resistance | Load = 1A | 75 | 140 | mΩ |