SNVS730C October   2011  – June 2019 LMR10520

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Ratings
    3. 6.3 Electrical Characteristics
    4. 6.4 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft-Start
      2. 7.3.2 Output Overvoltage Protection
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Current Limit
      5. 7.3.5 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
        2. 8.2.1.2 Inductor Selection
        3. 8.2.1.3 Input Capacitor
        4. 8.2.1.4 Output Capacitor
        5. 8.2.1.5 Catch Diode
        6. 8.2.1.6 Output Voltage
        7. 8.2.1.7 Calculating Efficiency and Junction Temperature
      2. 8.2.2 Application Curves
      3. 8.2.3 Other System Examples
        1. 8.2.3.1 LMR10520X Design Example 1
        2. 8.2.3.2 LMR10510X Design Example 2
        3. 8.2.3.3 LMR10510Y Design Example 3
        4. 8.2.3.4 LMR10510Y Design Example 4
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Definitions
    4. 9.4 WSON Package
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Layout Guidelines

When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most important consideration is the close coupling of the GND connections of the input capacitor and the catch diode D1. Place these ground ends close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. Next in importance is the location of the GND connection of the output capacitor, which should be near the GND connections of CIN and D1. There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. Place the feedback resistors as close as possible to the IC, with the GND of R1 placed as close as possible to the GND of the IC. Route the VOUT trace to R2 away from the inductor and any other traces that are switching. High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor. The remaining components should also be placed as close as possible to the IC. See

Application Note AN-1229 for further considerations and the LMR10520 demo board as an example of a good layout.