SNVSAG4B November   2015  – December 2024 LMR14020-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed Frequency Peak Current Mode Control
      2. 6.3.2  Slope Compensation
      3. 6.3.3  Sleep Mode
      4. 6.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 6.3.5  Adjustable Output Voltage
      6. 6.3.6  Enable and Adjustable Undervoltage Lockout
      7. 6.3.7  External Soft-start
      8. 6.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 6.3.9  Power Good (PGOOD)
      10. 6.3.10 Overcurrent and Short-Circuit Protection
      11. 6.3.11 Overvoltage Protection
      12. 6.3.12 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 CCM Mode
      4. 6.4.4 Light Load Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Set-Point
        2. 7.2.2.2 Switching Frequency
        3. 7.2.2.3 Output Inductor Selection
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Schottky Diode Selection
        6. 7.2.2.6 Input Capacitor Selection
        7. 7.2.2.7 Bootstrap Capacitor Selection
        8. 7.2.2.8 Soft-start Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
      2. 8.2.2 Related Products
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.8 Switching Frequency and Synchronization (RT/SYNC)

The switching frequency of the LMR14020-Q1 can be programmed by the resistor RT from the RT/SYNC pin and GND pin. The RT/SYNC pin can’t be left floating or shorted to ground. To determine the timing resistance for a given switching frequency, use Equation 5 or the curve in Figure 6-4. Table 6-1 gives typical RT values for a given fSW.

Equation 5. LMR14020-Q1
LMR14020-Q1 RT vs Frequency CurveFigure 6-4 RT vs Frequency Curve
Table 6-1 Typical Frequency Setting RT Resistance
fSW (kHz)RT (kΩ)
200133
35073.2
50049.9
75032.4
100023.2
150015.0
191211.5
22009.76

The LMR14020-Q1 switching action can also be synchronized to an external clock from 250 kHz to 2.3 MHz. Connect a square wave to the RT/SYNC pin through either circuit network shown in Figure 6-5. Internal oscillator is synchronized by the falling edge of external clock. The recommendations for the external clock include: high level no lower than 1.7 V, low level no higher than 0.5 V and have a pulse width greater than 30 ns. When using a low impedance signal source, the frequency setting resistor RT is connected in parallel with an AC coupling capacitor CCOUP to a termination resistor RTERM (that is, 50 Ω). The two resistors in series provide the default frequency setting resistance when the signal source is turned off. A 10 pF ceramic capacitor can be used for CCOUP. Figure 6-6, Figure 6-7 and Figure 6-8 show the device synchronized to an external system clock.

LMR14020-Q1 Synchronizing to an External ClockFigure 6-5 Synchronizing to an External Clock
LMR14020-Q1 Synchronizing in CCMFigure 6-6 Synchronizing in CCM
LMR14020-Q1 Synchronizing in Sleep ModeFigure 6-8 Synchronizing in Sleep Mode
LMR14020-Q1 Synchronizing in DCMFigure 6-7 Synchronizing in DCM

For spread spectrum option, the internal frequency dithering is disabled if the device is synchronized to an external clock.

Equation 6 calculates the maximum switching frequency limitation set by the minimum controllable on time and the input to output step down ratio. Setting the switching frequency above this value causes the regulator to skip switching pulses to achieve the low duty cycle required at maximum input voltage.

Equation 6. LMR14020-Q1

where

  • IOUT = Output current
  • RIND = Inductor series resistance
  • VIN_MAX = Maximum input voltage
  • VOUT = Output voltage
  • VD = Diode voltage drop
  • RDS_ON = High-side MOSFET switch on resistance
  • tON = Minimum on time