SNVSAA6A February   2015  – March 2015 LMR14050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency Peak Current Mode Control
      2. 8.3.2  Slope Compensation
      3. 8.3.3  Sleep-mode
      4. 8.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 8.3.5  Adjustable Output Voltage
      6. 8.3.6  Enable and Adjustable Under-voltage Lockout
      7. 8.3.7  External Soft-start
      8. 8.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 8.3.9  Over Current and Short Circuit Protection
      10. 8.3.10 Overvoltage Protection
      11. 8.3.11 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Set-Point
        2. 9.2.2.2 Switching Frequency
        3. 9.2.2.3 Output Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Schottky Diode Selection
        6. 9.2.2.6 Input Capacitor Selection
        7. 9.2.2.7 Bootstrap Capacitor Selection
        8. 9.2.2.8 Soft-start Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

  1. The feedback network, resistor RFBT and RFBB, should be kept close to the FB pin. VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shielding layer .
  2. The input bypass capacitor CIN must be placed as close as possible to the VIN pin and ground. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the GND pin and PAD .
  3. The inductor L should be placed close to the SW pin to reduce magnetic and electrostatic noise.
  4. The output capacitor, COUT should be placed close to the junction of L and the diode D. The L, D, and COUT trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency.
  5. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the system ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the system ground plane
  6. For more detail on switching power supply layout considerations see Application Note AN-1149

11.2 Layout Example

LMR14050 layout_snvsa81.gif Figure 30. Layout