SNVSAH4C December   2015  – February 2018 LMR23610

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Load VIN = 12 V
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency Peak Current Mode Control
      2. 7.3.2 Adjustable Output Voltage
      3. 7.3.3 EN/SYNC
      4. 7.3.4 VCC, UVLO
      5. 7.3.5 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
      6. 7.3.6 Internal Compensation and CFF
      7. 7.3.7 Bootstrap Voltage (BOOT)
      8. 7.3.8 Overcurrent and Short-Circuit Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Feed-Forward Capacitor
        7. 8.2.2.7  Input Capacitor Selection
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  VCC Capacitor Selection
        10. 8.2.2.10 Undervoltage Lockout Setpoint
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

VCC, UVLO

The LMR23610 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal voltage for VCC is 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. A high-quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage should be placed as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be loaded, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23610.

VCC undervoltage lockout (UVLO) prevents the LMR23610 from operating until the VCC voltage exceeds 3.3 V (typical). The VCC UVLO threshold has 400 mV (typical) of hysteresis to prevent undesired shutdown due to temporary VIN drops.