SNVSAS5 March   2018 LMR23615-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Load, VIN = 12 V
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency Peak-Current-Mode Control
      2. 7.3.2  Adjustable Frequency
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  EN/SYNC
      5. 7.3.5  VCC, UVLO
      6. 7.3.6  Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions
      7. 7.3.7  Internal Compensation and CFF
      8. 7.3.8  Bootstrap Voltage (BOOT)
      9. 7.3.9  Overcurrent and Short-Circuit Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Feed-Forward Capacitor
        7. 8.2.2.7  Input Capacitor Selection
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  VCC Capacitor Selection
        10. 8.2.2.10 Undervoltage Lockout Setpoint
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.5 Output Capacitor Selection

Choose the output capacitor(s), COUT, with care because output capacitance directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the ESR of the output capacitors:

Equation 14. LMR23615-Q1 eq11_snvsa81.gif

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 15. LMR23615-Q1 equation_11_snvsah2.gif

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large-load increase uccurs, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The regulator control loop usually needs six or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for six clock cycles to maintain the output voltage within the specified range. Equation 16 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor resulting in an output voltage overshoot. Equation 17 calculates the minimum capacitance required to keep the voltage overshoot within a specified range.

Equation 16. LMR23615-Q1 equation_12_snvsah2.gif
Equation 17. LMR23615-Q1 equation17.gif

where

  • KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT)
  • IOL = Low level output current during load transient
  • IOH = High level output current during load transient
  • VUS = Target output voltage undershoot
  • VOS = Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and chose KIND = 0.4. Equation 14 yields ESR no larger than 83.3 mΩ and Equation 15 yields COUT no smaller than 0.9 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be calculated to be no smaller than 14 μF and 4.1 μF by Equation 16 and Equation 17, respectively. Consider of derating, one 33-μF, 16 V ceramic capacitor with 5 mΩ ESR is used.