SNVSAV8B June   2017  – August 2020 LMR23615

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Peak-Current-Mode Control
      2. 7.3.2  Adjustable Frequency
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable/Sync
      5. 7.3.5  VCC, UVLO
      6. 7.3.6  Minimum ON-Time, Minimum-OFF Time, and Frequency Foldback at Dropout Conditions
      7. 7.3.7  Internal Compensation and CFF
      8. 7.3.8  Bootstrap Voltage (BOOT)
      9. 7.3.9  Overcurrent and Short-Circuit Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Feedforward Capacitor
        7. 8.2.2.7  Input Capacitor Selection
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  VCC Capacitor Selection
        10. 8.2.2.10 Undervoltage Lockout Setpoint
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB with the best power-conversion performance, thermal performance, and minimized generation of unwanted EMI.

  1. The input bypass capacitor CIN must be placed as close as possible to the VIN and PGND pins. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the PGND pin and PAD.
  2. Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground.
  3. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB must be located close to the FB pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, ensure that the VOUT sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.
  4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.
  5. Have a single point ground connection to the plane. Route the ground connections for the feedback and enable components to the ground plane. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.
  6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
  7. Provide adequate device heat sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat sinking to keep the junction temperature below 125°C.